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PDF LTC4301 Data sheet ( Hoja de datos )
| Número de pieza | LTC4301 | |
| Descripción | Supply Independent Hot Swappable 2-Wire Bus Buffer | |
| Fabricantes | Linear Technology | |
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LTC4301www.DataSheet4U.com
Supply Independent Hot
Swappable 2-Wire Bus Buffer
FEATURES
■ Allows Bus Pull-Up Voltages Above or Below VCC
■ Bidirectional Buffer* for SDA and SCL Lines
Increases Fanout
■ Prevents SDA and SCL Corruption During Live Board
Insertion and Removal from Backplane
■ Isolates Input SDA and SCL Line from Output
■ 10kV Human Body Model ESD Protection
■ 1V Precharge On All SDA and SCL Lines
■ Supports Clock Stretching, Arbitration and
Synchronization
■ High Impedance SDA, SCL Pins for VCC = 0V
■ CS Gates Connection from Input to Output
■ Compatible with I2CTM, I2C Fast Mode and SMBus
Standards (Up to 400kHz Operation)
■ Small 8-Pin MSOP and DFN (3mm × 3mm) Packages
U
APPLICATIO S
■ Hot Board Insertion
■ Servers
■ Capacitance Buffer/Bus Extender
■ Desktop Computers
■ CompactPCITM and ATCA Systems
DESCRIPTIO
The LTC®4301 supply independent, hot swappable, 2-wire
bus buffer allows I/O card insertion into a live backplane
without corruption of the data and clock busses. In addi-
tion, the LTC4301 allows the VCC, SDAIN and SCLIN pull-
up voltage and the SDAOUT and SCLOUT pull-up voltage
to be independent from each other. Control circuitry
prevents the backplane from being connected to the card
until a stop bit or a bus idle is present. When the connec-
tion is made, the LTC4301 provides bidirectional buffer-
ing, keeping the backplane and card capacitances isolated.
During insertion, the SDA and SCL lines are precharged to
1V to minimize bus disturbances. When driven low, the CS
input pin allows the part to connect after a stop bit or bus
idle occurs. Driving CS high breaks the connection be-
tween SCLIN and SCLOUT and between SDAIN and
SDAOUT. The READY output pin indicates that the back-
plane and card sides are connected together.
The LTC4301 is offered in 8-pin DFN (3mm × 3mm) and
MSOP packages.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 7032051.
TYPICAL APPLICATIO
3.3V 5V
10k 10k
BACK_SCL
BACK_SDA
BACKPLANE
CONNECTOR
0.01µF
SCLIN
VCC
LTC4301
SCLOUT
SDAIN
5V
10k
CS
GND
SDAOUT
READY
4301 TA01
10k 10k
CARD_SCL
CARD_SDA
OUTPUT
SIDE
20pF
1V/DIV
CARD
Input-Output Connection
INPUT
SIDE
55pF
1µs/DIV
4301 TA01b
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1
1 page  
U
OPERATIO
Start-Up
When the LTC4301 first receives power on its VCC pin,
either during power-up or live insertion, it starts in an
undervoltage lockout (UVLO) state, ignoring any activity
on the SDA or SCL pins until VCC rises above 2.5V (typical).
This is to ensure that the part does not try to function until
it has enough voltage to do so.
During this time, the 1V precharge circuitry is active and
forces 1V through 200k nominal resistors to the SDA and
SCL pins. Because the I/O card is being plugged into a live
backplane, the voltage on the backplane SDA and SCL
busses may be anywhere between 0V and VCC. Precharging
the SCL and SDA pins to 1V minimizes the worst-case
voltage differential these pins will see at the moment of
connection, therefore minimizing the amount of distur-
bance caused by the I/O card.
Once the LTC4301 comes out of UVLO, it assumes that
SDAIN and SCLIN have been inserted into a live system
and that SDAOUT and SCLOUT are being powered up at
the same time as itself. Therefore, it looks for either a stop
bit or bus idle condition on the backplane side to indicate
the completion of a data transaction. When either one
occurs, the part also verifies that both the SDAOUT and
SCLOUT voltages are high. When all of these conditions
are met, the input-to-output connection circuitry is acti-
vated, joining the SDA and SCL busses on the I/O card with
those on the backplane.
Connection Circuitry
Once the connection circuitry is activated, the functional-
ity of the SDAIN and SDAOUT pins is identical. A low
forced on either pin at any time results in both pin voltages
being low. For proper operation, logic low input voltages
should be no higher than 0.4V with respect to the ground
pin voltage of the LTC4301. SDAIN and SDAOUT enter a
logic high state only when all devices on both SDAIN and
SDAOUT release high. The same is true for SCLIN and
SCLOUT. This important feature ensures that clock stretch-
ing, clock synchronization, arbitration and the acknowl-
edge protocol always work, regardless of how the devices
in the system are tied to the LTC4301.
Another key feature of the connection circuitry is that it
provides bidirectional buffering, keeping the backplane
LTC4301www.DataSheet4U.com
and card capacitances isolated. Because of this isolation,
the waveforms on the backplane busses look slightly
different than the corresponding card bus waveforms as
described here.
Input-to-Output Offset Voltage
When a logic low voltage, VLOW1, is driven on any of the
LTC4301’s data or clock pins, the LTC4301 regulates the
voltage on the other side of the device (call it VLOW2) at a
slightly higher voltage, as directed by the following
equation:
VLOW2 = VLOW1 + 75mV + (VCC/R) • 70Ω (typical)
where R is the bus pull-up resistance in ohms. For ex-
ample, if a device is forcing SDAOUT to 10mV where VCC
= 3.3V and the pull-up resistor R on SDAIN is 10k, then the
voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 70 =
108mV (typical). See the Typical Performance Character-
istics section for curves showing the offset voltage as a
function of VCC and R.
Propagation Delays
During a rising edge, the rise time on each side is deter-
mined by the bus pull-up resistor and the equivalent
capacitance on the line. If the pull-up resistors are the
same, a difference in rise time occurs which is directly
proportional to the difference in capacitance between
the two sides. This effect is displayed in Figure 1 for
VCC = 5V and a 10k pull-up resistor on each side (55pF on
one side and 20pF on the other). SDAIN and SCLIN are
pulled-up to 3.3V, and SDAOUT and SCLOUT are pulled-
up to 5V. Since the output side has less capacitance than
the input, it rises faster and the effective low to high
propagation delay is negative.
OUTPUT
SIDE
20pF
1V/DIV
INPUT
SIDE
55pF
1µs/DIV
4301 F01
Figure 1. Input-Output Connection
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LTC4301www.DataSheet4U.com
PACKAGE DESCRIPTIO
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
0.675 ±0.05
R = 0.115
TYP
5
0.38 ± 0.10
8
3.5 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PACKAGE
OUTLINE
0.200 REF
3.00 ±0.10 1.65 ± 0.10
(4 SIDES) (2 SIDES)
0.75 ±0.05
0.00 – 0.05
4
0.25 ± 0.05
(DD8) DFN 1203
1
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
8 7 65
0.52
(.0205)
REF
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.42 ± 0.038
(.0165 ± .0015)
TYP
0.65
(.0256)
BSC
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
DETAIL “A”
0° – 6° TYP
4.90 ± 0.152
(.193 ± .006)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
GAUGE PLANE
0.18
(.007)
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
1 234
1.10
(.043)
MAX
SEATING
PLANE 0.22 – 0.38
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
(.009 – .015)
TYP 0.65
(.0256)
BSC
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.86
(.034)
REF
0.127 ± 0.076
(.005 ± .003)
MSOP (MS8) 0204
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet LTC4301.PDF ] | |
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