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PDF HB56UW3272ETK-F Data sheet ( Hoja de datos )
| Número de pieza | HB56UW3272ETK-F | |
| Descripción | 256MB Buffered EDO DRAM DIMM 32-Mword X 72-bit | |
| Fabricantes | Elpida Memory | |
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HB56UW3272ETK-F
256MB Buffered EDO DRAM DIMM
32-Mword × 72-bit, 4k Refresh, 2 Bank Module
(36 pcs of 16M × 4 components)
E0100H10 (1st edition)
(Previous ADE-203-1124A (Z))
Jan. 31, 2001
Description
The HB56UW3272ETK belongs to 8-byte DIMM (Dual in-line Memory Module) family , and has been
developed an optimized main memory solution for 4 and 8-byte processor applications. The
HB56UW3272ETK is 32 M × 72 Dynamic RAM Module, mounted 36 pieces of 64-Mbit DRAM
(HM5165405) sealed in TSOP package and 2 pieces of 16-bit line driver sealed in TSSOP package. The
HB56UW3272ETK offers Extended Data Out (EDO) Page Mode as a high speed access mode. An outline of
the HB56UW3272ETK is 168-pin socket type package (dual lead out). Therefore, the HB56UW3272ETK
makes high density mounting possible without surface mount technology. The HB56UW3272ETK provides
common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module
board.
Features
www.DataSheet4U.com
• 168-pin socket type package (Dual lead out)
Outline : 133.35 mm (Length) × 53.34 mm (Height) × 4.00 mm (Thickness)
Lead pitch : 1.27 mm
• Single 3.3 V supply: 3.3 ± 0.3V
• High speed
Access time: tRAC = 50 ns/60 ns (max)
Access time: tCAC = 18 ns/20 ns (max)
• Low power dissipation
Active mode: 8.78 W/7.49 W (max)
Standby mode (TTL): 295.2 mW (max)
• JEDEC standard outline buffered 8-byte DIMM
• Buffered input except RAS and DQ
• 4-byte interleave enabled, dual address input (A0/B0)
• EDO page mode capability
This Product become EOL in August, 2005.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
1 page  
Block Diagram
HB56UW3272ETK-F
RE1
RE0
CE0
WE0
OE0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
www.DataSheet4UDD.QQc23o90m
DQ31
DQ32
DQ33
DQ34
DQ35
CAS RAS WE OE
I/O
I/O
I/O
D0
I/O
CAS RAS WE OE
I/O
I/O
I/O
D1
I/O
CAS RAS WE OE
I/O
I/O
I/O
D2
I/O
CAS RAS WE OE
I/O
I/O
I/O
D3
I/O
CAS RAS WE OE
I/O
I/O
I/O
D4
I/O
CAS RAS WE OE
I/O
I/O
I/O
D5
I/O
CAS RAS WE OE
I/O
I/O
I/O
D6
I/O
CAS RAS WE OE
I/O
I/O
I/O
D7
I/O
CAS RAS WE OE
I/O
I/O
I/O
D8
I/O
CE1
RE3
RE2
CE4
WE2
OE2
CAS RAS WE OE
I/O
I/O
I/O
I/O
DQ36
D18 DQ37
DQ38
DQ39
CAS RAS WE OE
I/O
I/O
I/O
I/O
DQ40
D19 DQ41
DQ42
DQ43
CAS RAS WE OE
I/O
I/O
I/O
I/O
DQ44
D20 DQ45
DQ46
DQ47
CAS RAS WE OE
I/O
I/O
I/O
I/O
DQ48
D21 DQ49
DQ50
DQ51
CAS RAS WE OE
I/O
I/O
I/O
I/O
DQ52
D22 DQ53
DQ54
DQ55
CAS RAS WE OE
I/O
I/O
I/O
I/O
DQ56
D23 DQ57
DQ58
DQ59
CAS RAS WE OE
I/O
I/O
I/O
I/O
DQ60
D24 DQ61
DQ62
DQ63
CAS RAS WE OE
I/O
I/O
I/O
I/O
DQ64
D25 DQ65
DQ66
DQ67
CAS RAS WE OE
I/O
I/O
I/O
I/O
DQ68
D26 DQ69
DQ70
DQ71
A0
B0
A1 to A11
VCC
VSS
0.22µF × 44pcs
D0 to D8 , D18 to D26
D9 to D17 , D27 to D35
D0 to D35
D0 to D35, 16-bit line driver
D0 to D35, 16-bit line driver
* D0 to D35 : HM5165405
: 16-bit line driver
CE5
CAS RAS WE OE
I/O
I/O
I/O
D9
I/O
CAS RAS WE OE
I/O
I/O
I/O
D10
I/O
CAS RAS WE OE
I/O
I/O
I/O
D11
I/O
CAS RAS WE OE
I/O
I/O
I/O
D12
I/O
CAS RAS WE OE
I/O
I/O
I/O
D13
I/O
CAS RAS WE OE
I/O
I/O
I/O
D14
I/O
CAS RAS WE OE
I/O
I/O
I/O
D15
I/O
CAS RAS WE OE
I/O
I/O
I/O
D16
I/O
CAS RAS WE OE
I/O
I/O
I/O
D17
I/O
CAS RAS WE OE
I/O
I/O
I/O
D27
I/O
CAS RAS WE OE
I/O
I/O
I/O
D28
I/O
CAS RAS WE OE
I/O
I/O
I/O
D29
I/O
CAS RAS WE OE
I/O
I/O
I/O
D30
I/O
CAS RAS WE OE
I/O
I/O
I/O
D31
I/O
CAS RAS WE OE
I/O
I/O
I/O
D32
I/O
CAS RAS WE OE
I/O
I/O
I/O
D33
I/O
CAS RAS WE OE
I/O
I/O
I/O
D34
I/O
CAS RAS WE OE
I/O
I/O
I/O
D35
I/O
PD1 to PD8
VCC
VSS
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
ID pin
VSS
VSS
0Ω
0Ω
PD1
PD2
PD3
PD4
0Ω
PD5
0Ω
PD6
0Ω
PD7
PD8
ID0
ID1
Data Sheet E0100H10
5
5 Page 
HB56UW3272ETK-F
EDO Page Mode Read-Modify-Write Cycle
Parameter
EDO page mode read- modify-write
cycle time
WE delay time from CAS precharge
50 ns
Symbol Min
t HPRWC
57
Max
—
t CPW
45
—
60 ns
Min
68
Max
—
54 —
Unit Notes
ns
ns 14
Refresh
Parameter
Symbol
Max
Unit Notes
Refresh period
tREF 64
ms 4096 cycles
Notes: 1. AC measurements assume tT = 2 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh).
www.DataSheet4U.com
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, than the access time is
controlled exclusively by tCAC.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that tRCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
11. Assumes that tRAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max).
12. Either tRCH or tRRH must be satisfied for a read cycles.
13. tOFF (max), tOEZ (max), tWEZ (max) and tOFR (max) define the time at which the outputs achieve the
open circuit condition and are not referred to output voltage levels.
14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle and the
data out pin will remain open circuit (high impedance) throughout the entire cycle; iftRWD ≥ tRWD (min),
tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW (min), the
cycle is a read-modify-write and the data output will contain data read from the selected cell; if
neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
15. tDS and tDH are referred to CAS leading edge in early write cycles and to WE leading edge in delayed
write or read-modify-write cycles.
16. tRASP defines RAS pulse width in EDO page mode cycles.
17. Access time is determined by the longest among tAA, tCAC and tCPA.
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data
to the device.
Data Sheet E0100H10
11
11 Page | ||
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| PDF Descargar | [ Datasheet HB56UW3272ETK-F.PDF ] | |
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