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PDF LTC4300A-3 Data sheet ( Hoja de datos )
| Número de pieza | LTC4300A-3 | |
| Descripción | Level Shifting Hot Swappable 2-Wire Bus Buffer | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
■ Bidirectional Buffer* for SDA and SCL Lines
Increases Fanout
■ Prevents SDA and SCL Corruption During Live
Board Insertion and Removal from Backplane
www.DataSh■eetL4Uo.gciocmThreshold ENABLE Input
■ Isolates Input SDA and SCL Lines from Output
■ Compatible with I2CTM, I2C Fast Mode and SMBus
Standards (Up to 400kHz Operation)
■ 1V Precharge on all SDA and SCL Lines
■ Supports Clock Stretching, Arbitration and
Synchronization
■ 5V to 3.3V Level Translation
■ High Impedance SDA, SCL Pins for VCC = 0V,
VCC2 = 0V
■ Small 8-Pin DFN and MSOP Packages
U
APPLICATIO S
■ Hot Board Insertion
■ Servers
■ Capacitance Buffer/Bus Extender
■ Desktop Computer
LTC4300A-3
Level Shifting
Hot Swappable 2-Wire
Bus Buffer with Enable
DESCRIPTIO
The LTC®4300A-3 hot swappable 2-wire bus buffer allows
I/O card insertion into a live backplane without corruption
of the data and clock busses. When the connection is
made, the LTC4300A-3 provides bidirectional buffering,
keeping the backplane and card capacitances isolated.
Rise-time accelerator circuitry allows the use of weaker
DC pull-up currents while still meeting rise-time require-
ments. During insertion, the SDA and SCL lines are
precharged to 1V to minimize bus disturbances.
The LTC4300A-3 provides level translation between 3.3V
and 5V supplies. The backplane and card can both be
powered with supplies ranging from 2.7V to 5.5V. The
LTC4300A-3 also incorporates a CMOS threshold ENABLE
pin which forces the part into a low current mode and iso-
lates the card from the backplane. When driven to VCC, the
ENABLE pin sets normal operation.
The LTC4300A-3 is available in the MSOP and 3mm × 3mm
DFN packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
*Patent pending.
TYPICAL APPLICATIO
VCC
3.3V
SCLIN
10k 10k
3
8
0.01µF
1
10k 10k
VCC2
0.01µF
2
SCLOUT
SDAIN
6
7
SDAOUT
OFF ON
5 LTC4300A-3
ENABLE GND
4
4300A-3 TA01
OUTPUT
SIDE
50pF
0.5V/DIV
Input–Output Connection
INPUT
SIDE
150pF
200ns/DIV
4300A TA02
sn4300a3 4300a3fs
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1 page  
LTC4300A-3
PI FU CTIO S
VCC2 (Pin 1): Card Supply Voltage. This is the supply
voltage for the devices on the card I2C busses. Connect
pull-up resistors from SDAOUT and SCLOUT to this pin.
Place a bypass capacitor of at least 0.01µF close to this pin
for best results.
SCLOUT (Pin 2): Serial Clock Output. Connect this pin to
the SCL bus on the card.
w w w . D a tSaCSLhIeNe(tP4inU .3c):oSmerial Clock Input. Connect this pin to the
SCL bus on the backplane.
GND (Pin 4): Device Ground. Connect this pin to a ground
plane for best results.
ENABLE (Pin 5): Digital CMOS Threshold Input. Ground-
ing this pin puts the part in a low current mode. It also
disables the rise-time accelerators, disables the bus
discharge circuitry, isolates SDAIN from SDOUT and
isolates SCLIN from SCLOUT. For active operation, drive
this pin to VCC. If this feature is unused, tie to VCC. Since
ENABLE is VCC referenced, do not connect to VCC2 or pull
up to VCC2.
SDAIN (Pin 6): Serial Data Input. Connect this pin to the
SDA bus on the backplane.
SDAOUT (Pin 7): Serial Data Output. Connect this pin to
the SDA bus on the card.
VCC (Pin 8): Main Input Power Supply from Backplane.
This is the supply voltage for the devices on the backplane
I2C busses. Connect pull-up resistors from SDAIN and
SCLIN to this pin. Place a bypass capacitor of at least
0.01µF close to this pin for best results.
Exposed Pad (Pin 9, DFN Package Only): Exposed Pad
may by be left open or connected to device ground.
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5 Page 
LTC4300A-3
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
0.675 ±0.05
R = 0.115
TYP
5
0.38 ± 0.10
8
3.5 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
www.DataSheet4U.com
PACKAGE
OUTLINE
PIN 1
TOP MARK
(NOTE 6)
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
0.200 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
0.00 – 0.05
4
0.25 ± 0.05
(DD8) DFN 1203
1
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
8 7 65
0.52
(.0205)
REF
0.889 ± 0.127
(.035 ± .005)
0.254
(.010)
DETAIL “A”
0° – 6° TYP
4.90 ± 0.152
(.193 ± .006)
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
0.42 ± 0.038
(.0165 ± .0015)
TYP
0.65
(.0256)
BSC
0.18
(.007)
SEATING
PLANE
RECOMMENDED SOLDER PAD LAYOUT
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
1 234
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP 0.65
(.0256)
BSC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
0.86
(.034)
REF
0.127 ± 0.076
(.005 ± .003)
MSOP (MS8) 0204
sn4300a3 4300a3fs
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11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet LTC4300A-3.PDF ] | |
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