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PDF SY89872U Data sheet ( Hoja de datos )
| Número de pieza | SY89872U | |
| Descripción | IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SY89872U (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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Micrel, Inc.
2.5V, 2GHz ANY DIFF. IN-TO-LVDS
PROGRAMMABLE CLOCK DIVIDER/FANOUT
Precision Edge®
Precision ESdY8g9e8®72U
BUFFER WITH INTERNAL TERMINATION
SY89872U
FEATURES
■ Guaranteed AC performance over temperature and
voltage:
Precision Edge®
• >2GHz fMAX
• < 750ps tPD (matched delay between banks)
• < 15ps within-device skew
DESCRIPTION
• < 200ps rise/fall time
■ Low jitter design
This 2.5V low-skew, low-jitter, precision LVDS output clock
divider accepts any high-speed differential clock input (AC
• < 1psRMS cycle-to-cycle jitter
• < 10psPP total jitter
■ Unique input termination and VT pin for DC-coupled
and AC-coupled inputs: any differential inputs
or DC-coupled) CML, LVPECL, HSTL or LVDS and divides
down the frequency using a programmable divider ratio to
create a frequency-locked, lower speed version of the input
clock. The SY89872U includes two output banks. Bank A is
(LVPECL, LVDS, CML, HSTL)
an exact copy of the input clock (pass through) with matched
■ Precision differential LVDS outputs
■ Matched delay: all outputs have matched delay,
independent of divider setting
■ TTL/CMOS inputs for select and reset/disable
propagation delay to Bank B, the divided output bank.
Available divider ratios are 2, 4, 8 and 16. In a typical
622MHz clock system this would provide availability of
311MHz, 155MHz, 77MHz or 38MHz auxiliary clock
components.
■ Two output banks (matched delay)
The differential input buffer has a unique internal
• Bank A: Buffered copy of input clock (undivided) termination design that allows access to the termination
• Bank B: Divided output (÷2, ÷4, ÷8, ÷16),
network through a VT pin. This feature allows the device to
two copies
easily interface to different logic standards. A VREF-AC
referencewww.DataSheet4U.com is included for AC-coupled applications.
■ 2.5V power supply
The SY89872U is part of Micrel’s high-speed Precision
■ Wide operating temperature range: –40°C to +85°C Edge® timing and distribution family. For 3.3V applications,
■ Available in 16-pin (3mm × 3mm) MLF® package
consider the SY89873L. For applications that require an
APPLICATIONS
LVPECL output, consider the SY89872U.
The /RESET input asynchronously resets the divider
■ OC-3 to OC-192 SONET/SDH applications
■ Transponders
■ Oscillators
outputs (Bank B). In the pass-through function (Bank A) the
/RESET synchronously enables or disables the outputs on
the next falling edge of IN (rising edge of /IN). Refer to the
“Timing Diagram.”
■ SONET/SDH line cards
FUNCTIONAL BLOCK DIAGRAM
TYPICAL APPLICATION
/RESET,
/DISABLE
Enable
FF
IN
50Ω
VT
50Ω
/IN
VREF-AC
S1
S0
Decoder
Enable
MUX
Divided
by
2, 4, 8
or 16
622MHz/155.5MHz
SONET Clock Generator
QA 622MHz LVPECL
QA 622MHz LVDS
/QA Clock In
/QA Clock Out
IN OC-12 or OC-3
QB0 /IN Clock Generator
QB 155.5MHz LVDS
/QB0 /QB Clock Out
QB1
/QB1 Bank A: 622MHz for OC-12 line card
Bank B: 155.5MHz for OC-3 line card (set to divide-by-4)
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
M9999-020707
[email protected] or (408) 955-1690
1
Rev.: D Amendment: /0
Issue Date: February 2007
1 page  
Micrel, Inc.
Precision Edge®
SY89872U
AC ELECTRICAL CHARACTERISTICS(Note 1, 2)
VCC = 2.5V ±5%; TA = –40°C to +85°C; Unless otherwise stated.
Symbol
Parameter
Condition
Min Typ Max Units
fMAX
Maximum Toggle Frequency
Maximum Input Frequency
Output Swing: ≥200mV
Note 3
2 GHz
3.2 GHz
tPD
Differential Propagation Delay
Input Swing: <400mV
IN to Q
Input Swing: ≥400mV
500 625 750
450 575 700
ps
ps
tSKEW
Within-Device Skew (differential)
(QB0-to-QB1)
Note 4
7 15 ps
Within-Device Skew (differential)
(Bank A-to-Bank B)
Note 4
12 30 ps
Part-to-Part Skew (differential)
Note 4
250 ps
trr
Tjitter
tr, tf
Reset Recovery Time
Cycle-to-Cycle Jitter
Total Jitter
Rise / Fall Time (20% to 80%)
Note 5
Note 6
Note 7
600 ps
1 psRMS
10 psPP
70 130 200 ps
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Note 7.
Measured with 400mV input signal, 50% duty cycle. 100Ω termination between Q and /Q, unless otherwise stated.
Specification packaged product only.
Bank A (pass-through) maximum frequency is limited by the output stage. Bank B (input-to-output ÷2, ÷4, ÷8, ÷16) can accept an input frequency
>3GHz, while Bank A will be slew rate limited.
Skew is measured between outputs under identical transitions.
See “Timing Diagram.”
Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. Tjitter_cc=Tn–Tn+1,
where T is the time between rising edges of the output signal.
Total jitter definition: with an ideal clock input, of frequency ≤ fMAX (device), no more than one output edge in 1012 output edges will deviate by
more than the specified peak-to-peak jitter value.
M9999-020707
[email protected] or (408) 955-1690
5
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