8312 반도체 회로 부품 판매점
1-to-12 LVCMOS/LVTTL Fanout Buffer
|
|
 IDT |
Low Skew, 1-to-12 LVCMOS/LVTTL
Fanout Buffer
8312
Datasheet
General Description
The 8312 is a low skew, 1-to-12 LVCMOS/ LVTTL Fanout Buffer
and a member of the family of High Performance Clock Solutions
from IDT. The 8312 single-ended clock input accepts LVCMOS or
LVTTL input levels. The low impedance LVCMOS outputs are
designed to drive 50 series or parallel terminated transmission
lines. The effective fanout can be increased from 12 to 24 by
utilizing the ability of the outputs to drive two series terminated
lines.
The 8312 is characterized at full 3.3V, 2.5V, and 1.8V, mixed
3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply
modes. Guaranteed output and part-to-part skew characteristics
along with the 1.8V output capabilities makes the 8312 ideal for
high performance, single ended applications that also require a
limited output voltage.
Features
• Twelve LVCMOS/LVTTL outputs
• CLK input supports the following input types: LVCMOS, LVTTL
• Maximum output frequency: 250MHz
• Output skew: 150ps (maximum)
• Supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
1.8V/1.8V
• 0°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
CLK_EN Pullup
CLK Pulldown
D
Q
LE
OE Pullup
12
Q[0:11]
©2015 Integrated Device Technology, Inc
1
Pin Assignment
GND
VDD
CLK_EN
CLK
GND
OE
VDD
GND
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
Q4
VDDO
Q5
GND
Q6
VDDO
Q7
GND
8312
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
December 11, 2015
8312 Datasheet
Table 1. Pin Descriptions
Number
1, 5, 8, 12, 16,
17, 21, 25, 29
2, 7
3
Name
GND
VDD
CLK_EN
4 CLK
6 OE
9, 11, 13, 15,
18, 20, 22, 24,
26, 28, 30, 32
10, 14, 19, 23,
27, 31
Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
VDDO
Type
Description
Power
Power supply ground.
Power
Input
Input
Input
Pullup
Pulldown
Pullup
Positive supply pins.
Synchronous control for enabling and disabling clock outputs.
LVCMOS / LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of outputs Q[0:11].
LVCMOS / LVTTL interface levels.
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN Input Capacitance
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
CPD
Power Dissipation Capacitance
(per output)
ROUT
Output Impedance
Test Conditions
VDDO = 3.465V
VDDO = 2.625V
VDDO = 2V
VDDO = 3.3V ± 5%
VDDO = 2.5V ± 5%
VDDO = 1.8V ± 0.2V
Minimum
Typical
4
51
51
7
7
10
Maximum
19
18
16
Units
pF
k
k
pF
pF
pF
©2015 Integrated Device Technology, Inc
2
December 11, 2015
|
국내 전력반도체 판매점
상호 : 아이지 인터내셔날
전화번호 : 051-319-2877
[ 홈페이지 ]
IGBT, TR 모듈, SCR, 다이오드모듈, 각종 전력 휴즈
( IYXS, Powerex, Toshiba, Fuji, Bussmann, Eaton )
전력반도체 문의 : 010-3582-2743
관련 데이터시트
831-91-016-10-001
PCB connectors 2.0 mm Single row / double row Solder tail - Precid-Dip Durtal SA
831-91-016-20-001
PCB connectors 2.0 mm Single row / double row Solder tail - Precid-Dip Durtal SA
831-91-016-30-001
PCB connectors 2.0 mm Single row / double row Surface mount - Precid-Dip Durtal SA
831-91-016-64-001
PCB connectors 2.0 mm Single row / double row Press-fit - Precid-Dip Durtal SA
831-93-016-10-001
PCB connectors 2.0 mm Single row / double row Solder tail - Precid-Dip Durtal SA
831-93-016-20-001
PCB connectors 2.0 mm Single row / double row Solder tail - Precid-Dip Durtal SA
831-93-016-30-001
PCB connectors 2.0 mm Single row / double row Surface mount - Precid-Dip Durtal SA
831-93-016-64-001
PCB connectors 2.0 mm Single row / double row Press-fit - Precid-Dip Durtal SA
831-99-016-10-001
PCB connectors 2.0 mm Single row / double row Solder tail - Precid-Dip Durtal SA