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CD4010C 반도체 회로 부품 판매점

Hex Buffers (Non-Inverting)



Fairchild Semiconductor 로고
Fairchild Semiconductor
CD4010C 데이터시트, 핀배열, 회로
October 1987
Revised June 2000
CD4010C
Hex Buffers (Non-Inverting)
General Description
The CD4010C hex buffers are monolithic complementary
MOS (CMOS) integrated circuits. The N- and P-channel
enhancement mode transistors provide a symmetrical cir-
cuit with output swings essentially equal to the supply volt-
age. This results in high noise immunity over a wide supply
voltage range. No DC power other than that caused by
leakage current is consumed during static conditions. All
inputs are protected against static discharge. These gates
may be used as hex buffers, CMOS to DTL or TTL inter-
face or as CMOS current drivers. Conversion ranges are
from 3V to 15V providing VCC VDD. The devices also
have buffered outputs which improve transfer characteris-
tics by providing very high gain.
Features
s Wide supply voltage range: 3.0V to 15V
s Low power: 100 nW (typ.)
s High noise immunity: 0.45 VDD (typ.)
s High current sinking: 8 mA (min.) at VO = 0.5V
capability: and VDD = 10V
Applications
• Automotive
• Data terminals
• Instrumentation
• Medical electronics
• Alarm system
• Industrial controls
• Remote metering
• Computers
Ordering Code:
Order Number Package Number
Package Description
CD4010CM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150Narrow
CD4010CN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
Connection Diagram
Schematic Diagram
Pin Assignments for DIP and SOIC
Top View
Hex COS/MOS to DTL or TTL
converter (inverting).
Connect VCC to DTL or TTL supply.
Connect VDD to COS/MOS supply.
© 2000 Fairchild Semiconductor Corporation DS005945
www.fairchildsemi.com


CD4010C 데이터시트, 핀배열, 회로
Absolute Maximum Ratings(Note 1)
Voltage at Any Pin (Note 2)
Operating Temperature Range
VSS 0.3V to VSS +15.5V
45°C to +85°C
Storage Temperature Range (TS)
Power Dissipation (PD)
Dual-In-Line
65°C to +150°C
700 mW
Small Outline
500 mW
Lead Temperature (TL)
(Soldering, 10 seconds)
260°C
Operating Range (VDD)
VSS + 3V to VSS + 15V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage
to the device may occur. Operating Ratings indicate conditions for which
the device is functional, but do not guarantee specific performance limits.
Note 2: This device should not be connected to circuits with the power on
because high transient voltage may cause permanent damage.
DC Electrical Characteristics
Test Conditions
Symbol
Characteristics
(Volts)
VO VDD
ICC Quiescent Device
Current
5
10
PD Quiescent Device
Dissipation/Package
5
10
Output Voltage
5
VOL LOW Level
VOH HIGH Level
10
5
10
Noise Immunity
(All Inputs)
VNL
VNH
Output Drive Current
VO 1.5
VO 3.0
VO 3.5
VO 7.0
0.4
5
10
5
10
5
IDN N-Channel (Note 3)
IDP P-Channel (Note 3)
0.5 10
2.5 5
9.5 10
IIN Input Current
Note 3: IDN and IDP are tested one output at a time.
40°C
Min Max
3
5
15
50
0.01
0.01
4.99
9.99
Min
4.99
9.99
Limits
+25°C
Typ
0.03
0.05
0.15
0.5
0
0
5
10
Max
3
5
15
50
0.01
0.01
+85°C
Min Max
42
70
210
700
0.05
0.05
4.95
9.95
Units
µA
µA
µW
µW
V
V
V
V
1.6
3.2
1.4
2.9
3.6
9.6
1.5
0.72
1.5
3
1.5
3
3
8
1.25
0.6
2.25
4.5
2.25
4.5
10
1.4
2.9
1.5
3
2.4
6.4
1
0.48
V
V
V
V
mA
mA
mA
mA
pA
www.fairchildsemi.com
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CD4010C buffer

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