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PDF APA3163 Data sheet ( Hoja de datos )
| Número de pieza | APA3163 | |
| Descripción | 20W Stereo Digital Class-D Audio Power Amplifier | |
| Fabricantes | ANPEC | |
| Logotipo |  |
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APA3163
20W Stereo Digital Class-D Audio Power Amplifier with EQ and DRC
Features
General Description
• Operating Voltage: 8.0V~24V for PVDD
The APA3163 is a digital input, stereo, high efficiency,
– 3.0V~3.6V for DVDD and AVDD
• High Efficiency Class-D Operation Eliminate the
Class-D audio amplifier available in a TQFP7x7-48P
package.
Need of Heatsinks
The APA3163 accepts the digital serial audio data and
• Digital Serial Audio Input (Stereo Output)
using the digital audio processor to convert the audio
• I2C Control Interface
data becomes the stereo Class-D output speaker
• Sampling Rate can Support from 32kHz to 192kHz amplifier. This provides the seamless integration between
• Separated Volume Control from 24dB to Mute
the codec and the speaker amplifier.
• Soft Mute (50% Duty Cycle)
The APA3163 is a slave device receiving clocks from ex-
• Programmable Dynamic Range Compression
ternal source, and the Class-D’s PWM switching fre-
– Power Limiter
quency is 352.8kHz for the sampling rate 44.1kHz or 384
– Speaker Protection
kHz for sampling 48kHz, depend on the input signal’s
– Night-Mode Listening
sampling rate.
• Programmable Biquads for Speaker EQ
• Shutdown and Mute Function
Pin Configuration
• Thermal and Over-Current Protections with Auto-
Recovery
• Space Saving Package TQFP7x7-48P
• Lead Free and Green Devices Available
(RoHS Compliant)
Applications
• LCD TV
Simplified Application Circuit
OUT_A 1
PVDD_A 2
PVDD_A 3
ABS 4
GDREG 5
NC 6
NC 7
TM 8
AVSS 9
PLL_LF
NC 11
NC 12
Digital Audio
Source
I2C
Control
MCLK
LRCLK
SCLK
SDIN
OUT_A
OUT_B
APA3163
OUT_C
SDA
SCL
OUT_D
Left
Channel
Speaker
Right
Channel
Speaker
TOP VIEW
(APA3163)
36 OUT_D
35 PVDD_D
34 PVDD_D
33 DBS
32 GDREG
31 DVREG
30 AGND
29 GND
28 DVSS
27 DVDD
26 TP3
25 RST
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
Rev. A.2 - Jan., 2013
1
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
1 page  
APA3163
Serial Audio Ports Slave Mode
Over recommended operating conditions (unless otherwise noted)
Symbol
Parameter
fSCLK
tSetup1
tHold1
Frequency, SCLK 32xfS, 48xfS,
64xfS
Setup Time, LRCLK to SCLK
Rising Edge
Hold Time, LRCLK to SCLK
Rising Edge
Test Conditions
CL=30pF
APA3163
Min.
Typ.
Max.
1.024
- 12.288
10 -
-
10 -
-
Unit
MHz
ns
Serial Audio Ports Slave Mode
Over recommended operating conditions (unless otherwise noted)
Symbol
Parameter
tSetup2
tHold
t(edge)
tr/tf
(SCLK/LRCLK)
Setup Time, SDIN to SCLK
Rising Edge
Hold Time, SDIN to SCLK Rising
Edge
LRCLK Frequency
LRCLK Duty Cycle
SCLK Duty Cycle
SCLK Rising Edges Between
LRCLK Riding Edges
LRCLK Clock Edge With Respect
To The Falling Edge of SCLK
Rise/Fall Time for SCLK/LRCLK
Test Conditions
APA3163
Min.
Typ.
Max.
10 -
-
10 -
-
8K 48K 48K
40 50 60
40 50 60
32 - 64
-1/4 -
1/4
- -8
Unit
ns
kHz
%
SCLK
edges
SCLK
period
ns
Reset Timing
Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to “Rec-
ommended Use Model” section on usage of all terminals.
Symbol
Parameter
tp(RST)
td(12C_Ready)
Pulse Duration, RST Active.
Time to Enable I2C
Test Conditions
No Load
Min.
100
-
APA3163
Typ.
-
-
Max.
-
13.5
Unit
µs
ms
Copyright © ANPEC Electronics Corp.
Rev. A.2 - Jan., 2013
5
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
5 Page 
APA3163
Typical Application Circuit
470 O 0.047 µF
4700pF
470 O 0.047µF
4700 pF
2200 pF
10µ F
0O
A_SEL
MCLK
0. 1µ F
4.7µ F
AVDD
/PDN
LRCK
SCLK
SDIN
SDA
SCL
AVDD
0.1 µF
AVDD
/ERROR
13
14
10kO MCLK
18.2kO TP1
15
16
10 kO
TP2
1V8_DV
17
18
/SD 19
LRCLK 20
SCLK 21
SDIN 22
SDA 23
SCL 24
APA3163
1 µF
0.033µ F
PVDD
22µH
0.1µ F
220µ F
0. 68µF
48
47
46
45
44
43
42
41
40
39
38
37
PGND_AB
PGND_AB
OUT_B
PVDD_B
PVDD_B
BBS
DBS
PVDD_C
PVDD_C
OUT_C
PGND_CD
PGND_CD
PVDD
0. 68µF
22µH
0.033µ F
0.033µ F
0.1µ F
0.1µ F
22µH
0. 68µF
/RESET
10µ F
DVDD
0 .1 µF
0.1µ F
0.1µ F
0.033 µF
1µF
220µ F
22µH
0. 68µF
8O
PVDD
8O
Copyright © ANPEC Electronics Corp.
Rev. A.2 - Jan., 2013
11
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet APA3163.PDF ] | |
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