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PDF SY88883V Data sheet ( Hoja de datos )
| Número de pieza | SY88883V | |
| Descripción | CML LOW-POWER LIMITING POST AMPLIFIER | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SY88883V (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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Micrel, Inc.
3.3V/5V 3.2Gbps CML LOW-POWER
LIMITING POST AMPLIFIER WITH TTL SD
SY88883V
SY88883V
FEATURES
DESCRIPTION
s Multi-rate up to 3.2Gbps operation
The SY88883V low-power, limiting post amplifier is
s Wide gain-bandwidth product
• 38dB differential gain
• 2.2GHz 3dB bandwidth
s Low noise 50Ω CML data outputs
• 800mVPP output swing
• 60ps edge rates
• 5psRMS typ. random jitter
• 15psPP typ. deterministic jitter
s Chatter-free Signal Detect (SD) output
• 4.6dB electrical hysteresis
• OC-TTL output with internal 5kΩ pull-up resistor
designed for use in fiber optic receivers. The device connects
to typical transimpedance amplifiers (TIAs). The linear signal
output from TIAs can contain significant amounts of noise
and may vary in amplitude over time. The SY88883V
quantizes these signals and outputs typically 800mVPP
voltage-limited waveforms.
The SY88883V operates from a single +3.3V ±10% or
+5V ±10% power supply, over the industrial temperature
range of –40°C to +85°C. With its wide bandwidth and high-
gain, signals with data rates up to 3.2Gbps and as small as
10mVpp can be amplified to drive devices with CML inputs
or AC-coupled PECL inputs.
s Programmable SD sensitivity using single external
The SY88883V generates a signal detect (SD) open-
resistor
collector TTL output with internal 5kΩ pull-up resistor. A
s Internal 50Ω data input termination
s Wide operating range
• Single 3.3V ±10% or 5V ±10% power supply
• –40°C to +85°C industrial temperature range
s Available in a tiny 10-pin MSOP (3mm × 3mm)
package
programmable signal detect level set pin (SDLVL) sets the
sensitivity of the input amplitude detection. SD asserts high
if the input amplitude rises above the threshold set by SDLVL
and de-asserts low otherwise. Typically 4.6dB SD hysteresis
is provided to prevent chattering.
All support documentation can be found on Micrel’s web
site atwww.DataSheet4U.com www.micrel.com.
APPLICATIONS
s 1.25Gbps and 2.5Gbps Gigabit Ethernet
s 1.062Gbps and 2.125Gbps Fibre Channel
s 155Mbps, 622Mbps, 1.25Gbps and 2.5Gbps
SONET/SDH
s Gigabit interface converter (GBIC)
s Small form factor (SFF) and small form factor
pluggable (SFP) transceivers
s Parallel 10G Ethernet
s High-gain line driver and line receiver
TYPICAL PERFORMANCE
3.3V, 25°C, 10mVPP Input
@2.5Gbps 223–1 PRBS, RLOAD = 50Ω to VCC
FUNCTIONAL BLOCK DIAGRAM
DIN
50Ω
/DIN
VCC
GND
Limiting
Amplifer
VCC
–1.3V
2.8kΩ
SDLVL
CML
Buffer
DOUT
/DOUT
Level
Detect
VCC
5kΩ
OC-TTL
Buffer
SD
TIME (100ps/div.)
M9999-081005
[email protected] or (408) 955-1690
1
Rev.: B Amendment: /0
Issue Date: August 2005
1 page  
Micrel, Inc.
SY88883V
DETAILED DESCRIPTION
The SY88883V low-power limiting post amplifier operates
from a single +3.3V or +5V power supply, over temperatures
from –40°C to +85°C. Signals with data rates up to 3.2Gbps
and as small as 10mVPP can be amplified. Figure 1 shows
the allowed input voltage swing. The SY88883V generates
an SD output. SDLVL sets the sensitivity of the input
amplitude detection.
Input Amplifier/Buffer
The SY88883V’s inputs are internally terminated with 50Ω
to an internal reference voltage (VREF). VREF is typically
1.3V below VCC. Unless not affected by this internal
termination scheme, upstream devices need to be
AC-coupled to the SY88883V’s inputs. Figure 2 shows a
simplified schematic of the input stage.
The high-sensitivity of the input amplifier allows signals
as small as 10mVPP to be detected and amplified. The
input amplifier allows input signals as large as 1800mVPP.
Input signals are linearly amplified with a typically 38dB
differential voltage gain. Since it is a limiting amplifier, the
SY88883V outputs typically 800mVPP voltage-limited
waveforms for input signals that are greater than 10mVPP.
Applications requiring the SY88883V to operate with high-
gain should have the upstream TIA placed as close as
possible to the SY88883V’s input pins to ensure the best
performance of the device.
Output Buffer
The SY88883V’s CML output buffer is designed to drive
50Ω lines. The output buffer requires appropriate termination
for proper operation. An external 50Ω resistor to VCC or
equivalent for each output pin provides this. Figure 3 shows
a simplified schematic of the output stage and includes an
appropriate termination method. Of course, driving a
downstream device with a CML input that is internally
terminated with 50Ω to VCC eliminates the need for external
termination. As noted in the previous section, the amplifier
outputs typically 800mVPP waveforms across 25Ω total
loads. The output buffer, thus, switches typically 16mA tail-
current. Figure 4 shows the power supply current
measurement which excludes the 16mA tail-current.
Signal Detect
The SY88883V generates a chatter-free signal detect
(SD) open-collector TTL output with internal 5kΩ pull-up
resistor as shown in Figure 5. SD is used to determine that
the input amplitude large enough to be considered a valid
input. SD asserts high if the input amplitude rises above the
threshold set by SDLVL and deasserts low otherwise.
Typically 4.6dB SD hysteresis is provided to prevent
chattering.
Signal Detect-Level Set
A programmable signal detect-level set pin (SDLVL) sets
the threshold of the input amplitude detection. Connecting
an external resistor between VCC and SDLVL sets the voltage
at SDLVL. This voltage ranges from VCC to VREF. The
external resistor creates a voltage divider between VCC and
VREF as shown in Figure 6. If desired, an appropriate
external voltage may be applied rather than using a resistor.
The smaller the external resistor, implying a smaller voltage
difference from SDLVL to VCC, lowers the SD sensitivity.
Hence, larger input amplitude is required to assert SD.
“Typical Operating Characteristics” shows the relationship
between the input amplitude detection sensitivity and the
SDLVL setting resistor.
Hysteresis
The SY88883V provides typically 4.6dB SD electrical
hysteresis. By definition, a power ratio measured in dB is
10log(power ratio). Power is calculated as V2IN/R for an
electrical signal. Hence, the same ratio can be stated as
20log(voltage ratio). While in linear mode, the electrical
voltage input changes linearly with the optical power and,
hence, the ratios change linearly. Therefore, the optical
hysteresis in dB is half the electrical hysteresis in dB given
in the data sheet. The SY88883V provides typically 2.3dB
SD optical hysteresis. As the SY88883V is an electrical
device, this data sheet refers to hysteresis in electrical terms.
With 4.6dB SD hysteresis, a voltage factor of 1.7 is required
to assert SD from its deassert level.
M9999-081005
[email protected] or (408) 955-1690
5
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| PDF Descargar | [ Datasheet SY88883V.PDF ] | |
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