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Mitsubishi |
MITSUBISHI<Dig.Ana.INTERFACE>
M62367GP
3V TYPE 8-BIT 8CH D-A CONVERTER WITH BUFFER AMPLIFIERS
DESCRIPTION
The M62367GP is a CMOS semiconductor IC has 8 channels of 8-
bit D-A converter. It is operable with a low supply voltage between
2.7~3.6V,and is easy to use due to serial data input,and 3-
pin(DI,CLK,LD)connection with microcomputer.
The IC also contains Do pin terminal,enabling cascade
connection,and therefore is suitable for automatic control in
combination with a microcomputer.
FEATURES
•Operable with a low voltage between 2.7~3.6V
•12-bit serial data input(connected via 3 pins:DI,CLK,LD)
•8 channels of R-2R and segment type high-performance 8-bit
D-A converters
•8 buffer operational amplifiers with full swing of output voltage
between Vcc and GND.
•High oscillation stability against the capacitive load of buffer
operational amplifiers.
PIN CONFIGURATION (TOP VIEW)
VSS
(VrefL)
Ao2
1
2
Ao3 3
Ao4 4
Ao5 5
Ao6 6
Ao7 7
VDD 8
(VrefU)
16 GND
15 Ao1
14 DI
13 CLK
12 LD
11 Do
10 Ao8
9 Vcc
Outline 16P2E-A
APPLICATION
Digtal-analog conversion in industrial or home-use
electronic equipment.
Automatic control in combination with EEPROM and
microcomputer(Substitute for conventional semi-fixed
resistor)
BLOCK DIAGRAM
GND
16
Ao1
15
-
8-BIT
R-2R + SEGMENT
D-A CONVERTER
8-BIT
LATCH
DI CLK LD
14 13
12
Do
11
12-BIT SHIFT REGISTER
D0 1 2 3 4 5 D7
D8 9 10 D11
ADDRESS
(8) DECODER
(8)
Ao8 Vcc
10 9
-
D-A
L
8-BIT
LATCH
8-BIT
R-2R + SEGMENT
D-A CONVERTER
-
1
Vss
(VrefL)
2
Ao2
L
D-A
-
3
Ao3
LL L
D-A D-A D-A
-- -
45
6
Ao4 Ao5 Ao6
MITSUBISHI
ELECTRIC
L
D-A
-
78
Ao7 VDD
(VrefU)
( 1 /5)
MITSUBISHI<Dig.Ana.INTERFACE>
M62367GP
3V TYPE 8-BIT 8CH D-A CONVERTER WITH BUFFER AMPLIFIERS
EXPLANATION OF TERMINALS
Pin No.
14
11
13
Symbol
DI
Do
CLK
12 LD
15 Ao1
2 Ao2
3 Ao3
4 Ao4
5 Ao5
6 Ao6
7 Ao7
10 Ao8
9 VCC
16 GND
8 VDD
1 VSS
Function
Serial data input terminal to input 12-bit long serial data
Terminal to output MSB data of 12-bit shift register
Shift clock input terminal.Input signal at DI pin is input to 12-bit shift register at rise of shift clock pulse
When H-level signal is input to this terminal.The value stored in 12-bit shift register is loaded
in decoder and D-A converter output register
8-bit D-A converter output terminal
Power supply terminal
GND terminal
D-A converter upper reference voltage input terminal
D-A converter lower reference voltage input terminal
BLOCK DIAGRAM FOR EXPLANATION OF TERMINALS
Vcc
9
GND
16
DI 14
CLK 13
12-BIT SHIFT REGISTER
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
11 Do
88
ADDRESS DECODER
1 2 34 567 8
12 LD
D0 ............ D7
8-BIT
1 LATCH
.............................................8
D0 ............
8-BIT
LATCH
D7
8-BIT
R-2R + SEGMENT
D-A CONVERTER
..............................................
8-BIT
R-2R + SEGMENT
D-A CONVERTER
-
...................................................................................................
-
8
VDD
(VrefU)
15
Ao1
MITSUBISHI
ELECTRIC
10 1
Ao8 Vss
(VrefL)
( 2 /5)
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