파트넘버.co.kr ZL30123 데이터시트 검색

ZL30123 전자부품 데이터시트



ZL30123 전자부품 회로 및
기능 검색 결과



ZL30123  

Zarlink Semiconductor
Zarlink Semiconductor

ZL30123

Low Jitter Line Card Synchronizer

ZL30123 SONET/SDH Low Jitter Line Card Synchronizer Data Sheet May 2006 A full Design Manual is available to qualified customers. To register, please send an email to [email protected]. Ordering Information ZL30123GGG 100 Pin CAB




관련 부품 ZL301 상세설명

ZL30146  

  
SyncE SONET/SDH Line Card PLL

ZL30146 SyncE SONET/SDH Line Card PLL Short Form Data Sheet Features • Synchronizes to standard telecom or Ethernet backplane clocks and provides jitter filtered output clocks for SONET/SDH, PDH and Ethernet network interface cards Supports the requirements of ITU-T G.8262 fo



Zarlink Semiconductor
Zarlink Semiconductor

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ZL30120  

  
SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer

ZL30120 SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer Data Sheet May 2006 A full Design Manual is available to qualified customers. To register, please send an email to [email protected]. Ordering Information ZL30120GGG 100 Pin CABGA Trays ZL30120GGG2 100 Pin CA



Zarlink Semiconductor
Zarlink Semiconductor

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ZL30119  

  
Low Jitter Line Card Synchronizer

ZL30119 SONET/SDH Low Jitter Line Card Synchronizer Data Sheet December 2005 A full Design Manual is available to qualified customers. To register, please send an email to [email protected]. Ordering Information ZL30119GGG 100 Pin CABGA Trays ZL30119GGG2 100 Pin CABGA*



Zarlink Semiconductor
Zarlink Semiconductor

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ZL30117  

  
SONET/SDH Low Jitter Line Card Synchronizer

ZL30117 SONET/SDH Low Jitter Line Card Synchronizer Data Sheet February 2006 A full Design Manual is available to qualified customers. To register, please send an email to [email protected]. Ordering Information ZL30117GGG 64 Pin CABGA Trays ZL30117GGG2 64 Pin CABGA* T



Zarlink Semiconductor
Zarlink Semiconductor

PDF



ZL30112  

  
SLIC/CODEC DPLL

ZL30112 SLIC/CODEC DPLL Data Sheet Features 19.44 MHz November 2007 • • • • • • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or input Provides 2.048 MHz and 8.192 MHz output clocks and an 8 kHz framing pulse Automatic entry and exit from freerun mode on reference fai



Zarlink Semiconductor
Zarlink Semiconductor

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ZL30110  

  
Telecom Rate Conversion DPLL

ZL30110 Telecom Rate Conversion DPLL Data Sheet Features • • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz Provides a range of output clocks: • • • 65.536 MHz TDM clock locked to the input reference General purpose 25 MHz fan-out to 6 outputs locked to the



Zarlink Semiconductor
Zarlink Semiconductor

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