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xr DECEMBER 2006 XRK799J93 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER REV. 1.0.1 GENERAL DESCRIPTION The XRK799J93 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it gener
xr JANAUARY 2005 PRELIMINARY XRK79892 REV. P1.0.1 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated. FEATURES GENERAL DESCRIPTION The XRK
xr MARCH 2005 PRELIMINARY XRK7988 REV. P1.0.1 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER device will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is el
xr MARCH 2005 PRELIMINARY XRK7955 REV. P1.0.1 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER be latched (H). If that CLK is the primary clock, the device will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance.
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