XC95108-10PQ100C
Xilinx
XC95108 In-System Programmable CPLD1
®
XC95108 In-System Programmable CPLD
1 1*
December 4, 1998 (Version 3.0)
Product Specification
Features
• • • • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 108 macrocells with 2400 usable gates Up to 108 user I/O pins 5 V in
XC95108-10PQ100I
XC95108 In-System Programmable CPLD1
®
XC95108 In-System Programmable CPLD
1 1*
December 4, 1998 (Version 3.0)
Product Specification
Features
• • • • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 108 macrocells with 2400 usable gates Up to 108 user I/O pins 5 V in-system programmable (ISP) - Endurance o
Xilinx
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