파트넘버.co.kr PLL650-05 데이터시트 검색

PLL650-05 전자부품 데이터시트



PLL650-05 전자부품 회로 및
기능 검색 결과



PLL650-05  

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PLL650-05

Low EMI Network LAN Clock

FEATURES • • • • w w• • • • • w • Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. 3 fixed outputs of 2




관련 부품 PLL650- 상세설명

PLL650-10  

  
Network LAN Clock

FEATURES • • • • • • • • w w Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. Two outputs fixed at 125MHz.. Zero PPM synthesis error in all clocks.



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PLL650-09  

  
Low Cost Network LAN Clock

FEATURES • • • • • • • • w w Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. 4 outputs fixed at 50MHz . Zero PPM synthesis error in all clocks. Ide



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PLL650-08  

  
Network LAN Clock Source

FEATURES • • • • • • • • w w Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. 1 output fixed at 100MHz , 1 output fixed at 125MHz . Zero PPM synthes



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PLL650-07  

  
Low COST Network LAN Clock SOURCE

FEATURES • • • • • • • • w w w Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. 2 outputs fixed at 50MHz, 2 outputs fixed at 25MHz . Zero PPM synth



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PLL650-06  

  
Network LAN Clock

FEATURES • • • • • • • • w• w w Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. One output fixed at 50MHz One selectable frequency output of 66.



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PLL650-04  

  
Low EMI Clock

m Preliminary PLL650-04 o c . EMI Clock for 10/100 PHY and Gigabit Ethernet Low U t4 e FEATURES PIN CONFIGURATION e hswing with 25-mA output drive • Full CMOS output S capability at TTL level. a t • Advanced, low power, sub-micron CMOS processes. a • 25 MHz .D fundamental crystal or clock inpu



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