PLL601-01
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Low Phase Noise PLL Clock Multiplierm o .c U 4 t e FEATURES e h • Full swing CMOS S outputs with 25 mA drive capability a at TTL levels. t 10-27MHz fundamental crystal or • Reference a clock. .D crystal load capacitor: no external • Integrated w load capacitor required. w • Output clocks
PLL601-15
Low Phase Noise PLL Clock Multiplierm o .c U 4 t e FEATURES e h • Full swing CMOS S outputs with 25 mA drive capability a at TTL levels. t 20-30MHz crystal or clock. • Reference a • Integrated crystal load capacitor: no external .D load capacitor required. w • Output clocks up to 150MHz at 3.3V. w • Low phase noise (-126dBc/
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PLL601-12
Dual Output PLL Clockm Preliminary PLL601-12 o c . Output PLL Clock with Selectable Odd Multiplier Dual U t4 FEATURES e PIN CONFIGURATION e (Top View) h • Selectable multipliers (x2.5, x2.75, x3, x4.25, x5, x5.5, x5.75, S x6, x6.25, x10, x11, x11.5, x12, a x12.5). t • Crystala range from 13MHz to 31MHz (see SelecD t
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PLL601-02
Low Phase Noise PLL Clock MultiplierFEATURES
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w
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Full swing CMOS outputs with 25 mA drive capability at TTL levels. Reference 10-27MHz crystal or clock. Integrated crystal load capacitor: no external load capacitor required. Output clocks up to 160MHz at 3.3V. Low phase noise (-126dBc/Hz
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