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Preliminary PLL520-88/-89 Low Phase Noise VCXO (9.5-65MHz) PIN CONFIGURATION FEATURES • • • • • • • 19MHz to 65MHz fundamental crystal input. Output range: 9.5MHz – 65MHz Complementary outputs: PECL or LVDS output. Selectable OE Logic (enable high or enable low
Preliminary PLL520-88/-89 Low Phase Noise VCXO (9.5-65MHz) PIN CONFIGURATION FEATURES • • • • • • • 19MHz to 65MHz fundamental crystal input. Output range: 9.5MHz – 65MHz Complementary outputs: PECL or LVDS output. Selectable OE Logic (enable high or enable low
PLL520-80 Low Phase Noise VCXO (9.5-65MHz) DIE CONFIGURATION OUTSEL0^ 65 mil FEATURES • • • • • • • • 19MHz to 65MHz fundamental crystal input. Output range: 9.5MHz – 65MHz Complementary outputs: PECL or LVDS output. Selectable OE Logic (enable high or enable
Preliminary PLL520-70 CMOS Low Phase Noise VCXO (for 45-90MHz Fund Xtal) DIE CONFIGURATION 65 mil (1550,1475) 19 18 17 16 25 26 24 23 22 21 20 FEATURES • • • • • • • 45MHz to 90MHz Fundamental Mode Crystal. Output range: 45MHz – 90MHz (no PLL). CMOS outputs. In
PLL520-38/-39 PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal) PIN CONFIGURATION VDD XIN XOUT N/C N/C OE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 N/C N/C GND CLKC VDD CLKT N/C N/C FEATURES • • • • • • • 65MHz to 130MHz Fundamental Mode Crystal. Output ra
PLL520-38/-39 PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal) PIN CONFIGURATION VDD XIN XOUT N/C N/C OE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 N/C N/C GND CLKC VDD CLKT N/C N/C FEATURES • • • • • • • 65MHz to 130MHz Fundamental Mode Crystal. Output ra
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