PLL205-14 전자부품 데이터시트

m Preliminary PLL205-54 o c . Programmable Clock Generator for VIA KT-266 Chipset U 4 t FEATURES PIN CONFIGURATION e e • Generates all clock frequencies for VIA KT266 h chipset. S a • Support one t pair of differential CPU clocks, one pair of a differential push-pull CPU clocks, 3 AGP and 10 PCI

m Preliminary PLL205-04 o c . Programmable Clock Generator for VIA KT-266 Chipset U 4 t e FEATURES PIN CONFIGURATION e h • Generates all clock frequencies for VIA KT266 S chipset. a t • Support one pair of differential CPU clocks, one a pair of differential push-pull CPU clocks, 3 AGP .D and 10

m Preliminary PLL205-16 o c . Programmable Clock Generator for VIA KT-266 Chipset U t4 FEATURES PIN CONFIGURATION e e frequencies for VIA KT266 • Generates all clock h chipset. S a • Support one t pair of differential CPU clocks, one pair of a differential push-pull CPU clocks, 3 AGP and D 10 PC

m PLL205-11 o c . Motherboard Clock Generator for AMD - K7 U t4 e FEATURES PIN CONFIGURATION e h • Generates all clock frequencies for VIA K7 chip S sets requiring ta multiple CPU clocks and high speed a SDRAM buffers. • Support pair of differential CPU clocks, one .D oneCPU, open-drain 6 PCI an

FEATURES • • w w• • • • • • • • w Generates all clock frequencies for VIA K7 chip sets requiring multiple CPU clocks and high speed SDRAM buffers. Support one pair of differential CPU clocks, one open-drain CPU, 6 PCI and 13 high-speed SDRAM buffers for 3-DIMM applications. On

m PLL205-13 o c . Motherboard Clock Generator for AMD - K7 U 4 t e FEATURES PIN CONFIGURATION e h • Generates all clock frequencies for VIA K7 chip S sets requiring ta multiple CPU clocks and high speed a SDRAM buffers. • Support one pair of differential CPU clocks, one .D 3.3V push-pull CPU, 6