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PLL130-68/-69 High Speed Translator Buffers: Single ended to PECL or LVDS FEATURES Differential PECL (PLL130-68) or LVDS (PLL130-69) output. • Accepts any single-ended REFIN input (with as low as 100mV swing). • Internal AC coupling of REFIN • Input range from 1.0MHz to 1.0 GHz. • No Vref re
PLL130-09 High Speed Translator Buffer to LVDS FEATURES • • • • • Differential LVDS output Single AC coupled input (min. 100mV swing). Input range from DC to 1.0 GHz. 2.5V to 3.3V operation. Available in 8-Pin SOIC or 3x3mm QFN. PIN CONFIGURATION (TOP VIEW) GND REF_IN 1 2 3 4 VDD 8 7 6
PLL130-08 High Speed Translator Buffer to PECL FEATURES • • • • • Differential PECL output Single AC coupled input (min. 100mV swing). Input range from DC to 1.0 GHz. 2.5V to 3.3V operation. Available in 8-Pin SOIC or 3x3mm QFN. PIN CONFIGURATION (TOP VIEW) GND REF_IN GND PECL 1 2 3 4 8
PLL130-07 High Speed Translator Buffer to CMOS (Selectable Drive) FEATURES CMOS output Selectable Drive capability (15pF or 30pF output load). • Single AC coupled input (min. 100mV swing). • Input range from DC to 200 MHz. • 2.5V to 3.3V operation. • Available in 8-Pin SOIC and 3x3mm QFN. ww
PLL130-68/-69 High Speed Translator Buffers: Single ended to PECL or LVDS FEATURES Differential PECL (PLL130-68) or LVDS (PLL130-69) output. • Accepts any single-ended REFIN input (with as low as 100mV swing). • Internal AC coupling of REFIN • Input range from 1.0MHz to 1.0 GHz. • No Vref re
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