|
Preliminary PLL103-53 DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS FEATURES Generates 30-output buffers from one input. Supports up to 4 DDR DIMMS or 3 SDR DIMMS and 2 DDR DIMMS. • Supports 266MHz DDR SDRAM. • One additional output for feedback. • Less than 5ns delay. • Skew between an
PLL103-11 Low Skew Buffers FEATURES Generates 13 copies of High-speed clock inputs. Supports up to three SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50% duty cycle with low jitter. • Less than 5ns delay. • Skew between any o
Preliminary PLL103-07 2 DIMM DDR Fanout Buffer FEATURES • Generates 12-output buffers from one input. • Supports VIA Pro266 DDR chipset. • Supports up to 2 DDR DIMMS. • Supports up to 400MHz DDR, SDRAMS. • One additional output for feedback. • 6 differential clock distribution. • Les
Preliminary PLL103-06 DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS FEATURES Generates 12-output buffers from one input. Supports up to 2 DDR DIMMS or 3 SDRAM DIMMS. • Supports 266MHz DDR SDRAM. • One additional output for feedback. • Less than 5ns delay. • Skew between any outputs is less
Preliminary PLL103-05 1-to-5 Clock Distribution Buffer FEATURES • • • • • • • 5 outputs identical to FIN. Low skew (< 250 ps between outputs). Input / Output frequency range 0 – 160 MHz 25mA drive capability at TTL levels. 70mA drive capability at CMOS levels. 3.3V operation. Avail
Preliminary PLL103-03 DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS FEATURES Generates 24-output buffers from one input. Supports up to 4 DDR DIMMS or 3 SDR DIMMS and 2 DDR DIMMS. • Supports 266MHz DDR SDRAM. • One additional output for feedback. • Less than 5ns delay. • Skew between an
|
사이트 맵 |
0 1 2 3 4 5 6 7 8 9 A B C |
PartNumber.co.kr | 2020 | 연락처 |