PLL102-10
PhaseLink Corporation
Low Skew Output BufferPLL102-10
Low Skew Output Buffer
FEATURES
Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to outputs. • Zero input - output delay. • Less than 700 ps device - device skew. • Less th
PLL102-108
PhaseLink Corporation
Programmable DDR Zero Delay Clock DriverPLL102-108
Programmable DDR Zero Delay Clock Driver
FEATURES
PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. • Distributes one clock Input to one bank of ten differential outputs. • Track spread spectrum clocking for E
PLL102-109
PhaseLink Corporation
Programmable DDR Zero Delay Clock DriverPreliminary
PLL102-109
Programmable DDR Zero Delay Clock Driver
FEATURES
PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. • Distributes one clock Input to one bank of six differential outputs. • Track spread spectrum