Datasheet PLL102-05 Equivalent ( PDF )

N.º	Número de pieza	Descripción	Fabricantes	PDF
1	PLL102-05	Low Skew Output Buffer PLL102-05 Low Skew Output Buffer FEATURES Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation). • Zero input - output delay. • Less than 700 ps device - device skew. • Less than 250	PhaseLink Corporation

PLL102 Datasheet ( Hoja de datos ) - resultados coincidentes

Número de pieza	Descripción	Fabricantes	PDF
PLL102-109	Programmable DDR Zero Delay Clock Driver Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver FEATURES PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. • Distributes one clock Input to one bank of six differential outputs. • Track spread spectrum clocking for EMI red	PhaseLink Corporation
PLL102-05	Low Skew Output Buffer PLL102-05 Low Skew Output Buffer FEATURES Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation). • Zero input - output delay. • Less than 700 ps device - device skew	PhaseLink Corporation
PLL102-15	Low Skew Output Buffer PLL102-15 Low Skew Output Buffer FEATURES Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spec trum modulation on reference clock to pass to the outputs (up to 33kHz SST modulation). • Zero input - output delay. • Less than 700 ps device - device skew	PhaseLink Corporation

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Número de pieza	Descripción	Fabricantes	PDF
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