파트넘버.co.kr PLL102-04 데이터시트 검색

PLL102-04 전자부품 데이터시트



PLL102-04 전자부품 회로 및
기능 검색 결과



PLL102-04  

PhaseLink Corporation
PhaseLink Corporation

PLL102-04

Low Skew Output Buffer

PLL102-04 Low Skew Output Buffer FEATURES Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation). • Zero input - output delay. • Less than 700 ps




관련 부품 PLL102- 상세설명

PLL102-15  

  
Low Skew Output Buffer

PLL102-15 Low Skew Output Buffer FEATURES Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spec trum modulation on reference clock to pass to the outputs (up to 33kHz SST modulation). • Zero input - output delay. • Less than 700 ps device - device skew. • Less than 250



PhaseLink Corporation
PhaseLink Corporation

PDF



PLL102-108  

  
Programmable DDR Zero Delay Clock Driver

PLL102-108 Programmable DDR Zero Delay Clock Driver FEATURES PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. • Distributes one clock Input to one bank of ten differential outputs. • Track spread spectrum clocking for EMI reduction. • Programmable delay bet



PhaseLink Corporation
PhaseLink Corporation

PDF



PLL102-10  

  
Low Skew Output Buffer

PLL102-10 Low Skew Output Buffer FEATURES Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to outputs. • Zero input - output delay. • Less than 700 ps device - device skew. • Less than 250 ps skew between outputs. www.Data



PhaseLink Corporation
PhaseLink Corporation

PDF



PLL102-03  

  
Low Skew Output Buffer

PLL102-03 Low Skew Output Buffer FEATURES Frequency range 75 ~ 180MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation). • Zero input - output delay. • Less than 700 ps device - device skew. • Less than 250



PhaseLink Corporation
PhaseLink Corporation

PDF



PLL102-109  

  
Programmable DDR Zero Delay Clock Driver

Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver FEATURES PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. • Distributes one clock Input to one bank of six differential outputs. • Track spread spectrum clocking for EMI reduction. • Programm



PhaseLink Corporation
PhaseLink Corporation

PDF



PLL102-05  

  
Low Skew Output Buffer

PLL102-05 Low Skew Output Buffer FEATURES Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation). • Zero input - output delay. • Less than 700 ps device - device skew. • Less than 250



PhaseLink Corporation
PhaseLink Corporation

PDF




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