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MACH221SP 전자부품 데이터시트



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MACH221SP  

Lattice Semiconductor
Lattice Semiconductor

MACH221SP

High-Performance EE CMOS Programmable Logic

MACH 1 and 2 CPLD Families High-Performance EE CMOS Programmable Logic FEATURES x High-performance electrically-erasable CMOS PLD families x 32 to 128 macrocells x 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages x SpeedLocking™ – guaranteed




관련 부품 MACH221 상세설명

MACH221-7  

  
High-Performance EE CMOS Programmable Logic

MACH 1 & 2 Families 1 FINAL MACH 1 & 2 FAMILIES COM’L: -7/10/12/15 IND: -10/-12/14/18 MACH221-7/10/12/15 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS x 68 Pins in PLCC x 96 Macrocells x 7.5 ns tPD Commercial, 10 ns tPD Industrial x 133 MHz fCNT x 48 I/Os; 4 dedicat



Vantis
Vantis

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MACH221-12  

  
High-Performance EE CMOS Programmable Logic

MACH 1 & 2 Families 1 FINAL MACH 1 & 2 FAMILIES COM’L: -7/10/12/15 IND: -10/-12/14/18 MACH221-7/10/12/15 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS x 68 Pins in PLCC x 96 Macrocells x 7.5 ns tPD Commercial, 10 ns tPD Industrial x 133 MHz fCNT x 48 I/Os; 4 dedicat



Vantis
Vantis

PDF



MACH221-10  

  
High-Performance EE CMOS Programmable Logic

MACH 1 & 2 Families 1 FINAL MACH 1 & 2 FAMILIES COM’L: -7/10/12/15 IND: -10/-12/14/18 MACH221-7/10/12/15 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS x 68 Pins in PLCC x 96 Macrocells x 7.5 ns tPD Commercial, 10 ns tPD Industrial x 133 MHz fCNT x 48 I/Os; 4 dedicat



Vantis
Vantis

PDF



MACH221-15  

  
High-Performance EE CMOS Programmable Logic

MACH 1 & 2 Families 1 FINAL MACH 1 & 2 FAMILIES COM’L: -7/10/12/15 IND: -10/-12/14/18 MACH221-7/10/12/15 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS x 68 Pins in PLCC x 96 Macrocells x 7.5 ns tPD Commercial, 10 ns tPD Industrial x 133 MHz fCNT x 48 I/Os; 4 dedicat



Vantis
Vantis

PDF



MACH221  

  
High-Performance EE CMOS Programmable Logic

MACH 1 and 2 CPLD Families High-Performance EE CMOS Programmable Logic FEATURES x High-performance electrically-erasable CMOS PLD families x 32 to 128 macrocells x 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages x SpeedLocking™ – guaranteed fixed timing up to 16 product terms x Co



Lattice Semiconductor
Lattice Semiconductor

PDF




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