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IDT74SSTUBF32865A  

IDT
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IDT74SSTUBF32865A

28-BIT 1:2 REGISTERED BUFFER

DATASHEET 28-BIT 1:2 REGISTERED BUFFER WITH PARITY IDT74SSTUBF32865A The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it wit




관련 부품 IDT74SSTUBF3286 상세설명

IDT74SSTUBF32869A  

  
14-BIT CONFIGURABLE REGISTERED BUFFER

DATASHEET 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 CONFIDENTIAL IDT74SSTUBF32869A Description The IDT74SSTUBF32869A is 14-bit 1:2 registered buffer with parity, designed for 1.7 V to 1.9 V VDD operation. All clock and data inputs are compatible with the JEDEC standard



IDT
IDT

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IDT74SSTUBF32868A  

  
28-BIT CONFIGURABLE REGISTERED BUFFER

DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 IDT74SSTUBF32868A occurred on the open-drain QERR pin (active low). The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity



IDT
IDT

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IDT74SSTUBF32866B  

  
25-BIT CONFIGURABLE REGISTERED BUFFER

DATASHEET 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 CONFIDENTIAL IDT74SSTUBF32866B Description This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for



IDT
IDT

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