|
Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer ICS8543I DATA SHEET General Description The ICS8543I is a low skew, high performance 1-to-4 Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8543I provides a low power, low noise, solution for
PRELIMINARY Integrated Circuit Systems, Inc. ICS8543 LOW SKEW, 1-TO-4 LVDS FANOUT BUFFER FEATURES • 4 LVDS outputs • Designed to meet or exceed the requirements of ANSI TIA/EIA-644 • Selectable differential HSTL or LVPECL clock inputs • LVCMOS / LVTTL control inputs • 3.3V operating suppl
Integrated Circuit Systems, Inc. ICS85408 LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP FEATURES • 8 Differential LVDS outputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 700MHz • Translate
Integrated Circuit Systems, Inc. ICS854057 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION FEATURES • High speed differential multiplexer. The device can be configured as either a 4:1 or 2:1 multiplexer • Single LVDS output • 4 selectable PCLK, nPCLK inputs with internal ter
8:1 Differential-to-LVDS Clock Multiplexer ICS854S058I DATASHEET General Description The ICS854S058I is an 8:1 Differential-to-LVDS Clock Multiplexer which can operate up to 2.5GHz. The ICS854S058I has 8 selectable differential clock inputs. The PCLK, nPCLK input pairs can accept LVPECL, LVDS, SS
4:1 Differential-to-LVDS Clock Multiplexer ICS854S054I DATA SHEET General Description The ICS854S054I is a 4:1 Differential-to-LVDS Clock Multiplexer which can operate up to 2.5GHz. The ICS854S054I has 4 selectable differential clock inputs. The PCLK, nPCLK input pairs can accept LVPECL, LVDS or C
|
사이트 맵 |
0 1 2 3 4 5 6 7 8 9 A B C |
PartNumber.co.kr | 2020 | 연락처 |