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PRELIMINARY INFORMATION ICS571 Low Phase Noise Zero Delay Buffer Features • Packaged in 8 pin SOIC. • Can function as low phase noise x2 multiplier. • Low skew outputs. One is ÷2 of other. • Input clock frequency up to 160 MHz at 3.3V. • Phase noise of better than -1
ICS574 Zero Delay, Low Skew Buffer Description The ICS574 is a low jitter, low-skew, high performance PLL-based zero delay buffer for high speed applications. Based on ICS’s proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at
ICS570A Multiplier and Zero Delay Buffer Description The ICS570A is a high performance Zero Delay Buffer (ZDB) which integrates ICS’ proprietary analog/digital Phase Locked Loop (PLL) techniques. ICS introduced the world standard for these devices in 1992 with the debut of the
DATASHEET MULTIPLIER AND ZERO DELAY BUFFER Description The ICS570-01 is a high-performance Zero Delay Buffer (ZDB) which integrates IDT’s proprietary mixed signal Phased Lock Loop (PLL) techniques. The zero delay feature means that the rising edge of the input clock aligns wi
ICS570 Multiplier and Zero Delay Buffer Description The ICS570 is a high-performance Zero Delay Buffer (ZDB) which integrates ICS’ proprietary analog/digital Phase Locked Loop (PLL) techniques. The A version is recommended for 5 V designs and the B version for 3.3 V designs. T
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