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HD74HCT245 Octal Bus Transceivers (with 3-state outputs) Description This device has an active low enable input G and a direction control input (DIR). When DIR is high, data flows from the A inputs to the B outputs. When DIR is low, data flows from the B inputs to the A outputs. The HD74HCT245 tran
HD74HCT242/HD74HCT243 Quad. Bus Transceivers (with 3-state outputs) Description The HD74HCT242 is an inverting buffer and the HD74HCT243 is a noninverting buffer. Each device has one active high enable (GBA), and one active low enable (GAB). GBA enables the A outputs and GAB enables the B outputs.
HD74HCT242/HD74HCT243 Quad. Bus Transceivers (with 3-state outputs) Description The HD74HCT242 is an inverting buffer and the HD74HCT243 is a noninverting buffer. Each device has one active high enable (GBA), and one active low enable (GAB). GBA enables the A outputs and GAB enables the B outputs.
HD74HCT241 Octal Buffers/Line Drivers/Line Receivers (with noninverted 3-state outputs) Description The HD74HCT241 is a noninverting buffer and has one active low enable and one active high enable. Each enable independently controls 4 buffers. This device does not have schmitt trigger inputs. Feat
HD74HCT238 3-to-8-line Decoder/Demultiplexer Description The HD74HCT238 has 3 binary select inputs (A, B, and C). If the device is enabled these inputs determined which one of the eight normally high outputs will go low. Two active low and one active high enables (G1, G2A and G2B) are provided to e
HD74HCT237 3-to-8-line Decoder/Demultiplexer with Address Latch Description The HD74HCT237 decodes a three-bit Address to one-of-eight active-high outputs. The device has a transparent latch for storage of the Address. Two Chip Selects, one active-low and one active-high, are provided to facilitate
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