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HD74HC245 Octal Bus Transceivers (with 3-state outputs) REJ03D0598–0200 (Previous ADE-205-475) Rev.2.00 Jan 31, 2006 Description Each device has an active low enable input G and a direction control input, DIR. When DIR is high, data flows from the A inputs to the B outputs. When DIR is low, dat
HD74HC240 Octal Buffers/Line Drivers/Line Receivers (with inverted 3-state outputs) REJ03D0594–0200 (Previous ADE-205-471) Rev.2.00 Jan 31, 2006 Description The HD74HC240 is an inverting buffer and has two active low enables (1G and 2G). Each enable independently controls 4 buffers. This device
HD74HC21 Dual 4-input AND Gates Features • High Speed Operation: tpd = 11 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C) �
HD74HC242/HD74HC243 Quad. Bus Transceivers (with 3-state outputs) Quad. Bus Transceivers (with noninverted 3-state outputs) Description The HD74HC242 is an inverting buffer and the HD74HC243 is a noninverting buffer. Each device has one active high enable (GBA), and one active low enable ( GAB). GB
HD74HC242/HD74HC243 Quad. Bus Transceivers (with 3-state outputs) Quad. Bus Transceivers (with noninverted 3-state outputs) Description The HD74HC242 is an inverting buffer and the HD74HC243 is a noninverting buffer. Each device has one active high enable (GBA), and one active low enable ( GAB). GB
HD74HC298 Quad. 2-input Multiplexers (with storage) Description This circuit is controlled by the signals word select and clock. When the word select input is taken low word 1 (A 1, B1, C1 and D 1) is presented to the inputs of the flip-flops, and when word select is high word 2 (A 2, B 2, C2 and D
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