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Datasheet EDS2532EGBH-TT Equivalent ( PDF ) |
N.º | Número de pieza | Descripción | Fabricantes | Category |
1 | EDS2532EGBH-TT | 256M bits SDRAM WTR
PRELIMINARY DATA SHEET
256M bits SDRAM
WTR (Wide Temperature Range) EDS2532EGBH-TT (8M words × 32 bits)
Specifications
• Density: 256M bits • Organization 2M words × 32 bits × 4 banks • Package: 90-ball FBGA Lead-free (RoHS compliant) and Halogen-free • Power | Elpida Memory | data |
EDS Datasheet ( Hoja de datos ) - resultados coincidentes |
N.º | Número de pieza | Descripción | Fabricantes | Catagory |
1 | EDS1216AABH | (EDS1216AABH / EDS1216CABH) 128M bits SDRAM (8M words x 16 bits)
DATA SHEET
128M bits SDRAM
EDS1216AABH, EDS1216CABH (8M words × 16 bits)
Description
The EDS1216AABH, EDS1216CABH are 128M bits SDRAM organized as 2,097,152 words × 16 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. Supply voltage Elpida Memory data | | |
2 | EDS1216AATA | 128M bits SDRAM
DATA SHEET
128M bits SDRAM
EDS1216AATA (8M words × 16 bits)
Description
The EDS1216AATA is a 128M bits SDRAM organized as 2,097,152 words × 16 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. It is packaged in 54-pin plastic TSOP ( Elpida Memory data | | |
3 | EDS1216CABH | (EDS1216AABH / EDS1216CABH) 128M bits SDRAM (8M words x 16 bits)
DATA SHEET
128M bits SDRAM
EDS1216AABH, EDS1216CABH (8M words × 16 bits)
Description
The EDS1216AABH, EDS1216CABH are 128M bits SDRAM organized as 2,097,152 words × 16 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. Supply voltage Elpida Memory data | | |
4 | EDS1232AABB | 128M bits SDRAM PRELIMINARY DATA SHEET
128M bits SDRAM
EDS1232AABB, EDS1232AATA (4M words × 32 bits)
Description
The EDS1232AA is a 128M bits SDRAM organized as 1,048,576 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. They are packaged in 90-ball FBGA, 86 Elpida Memory data | | |
5 | EDS1232AATA | 128M bits SDRAM PRELIMINARY DATA SHEET
128M bits SDRAM
EDS1232AABB, EDS1232AATA (4M words × 32 bits)
Description
The EDS1232AA is a 128M bits SDRAM organized as 1,048,576 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. They are packaged in 90-ball FBGA, 86 Elpida Memory data | | |
6 | EDS1232CABB | 128M bits SDRAM PRELIMINARY DATA SHEET
128M bits SDRAM
EDS1232CABB, EDS1232CATA (4M words × 32 bits)
Description
The EDS1232CA is a 128M bits SDRAM organized as 1,048,576 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. They are packaged in 90-ball FBGA, 86 Elpida Memory data | | |
7 | EDS1232CATA | 128M bits SDRAM PRELIMINARY DATA SHEET
128M bits SDRAM
EDS1232CABB, EDS1232CATA (4M words × 32 bits)
Description
The EDS1232CA is a 128M bits SDRAM organized as 1,048,576 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. They are packaged in 90-ball FBGA, 86 Elpida Memory data | |
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Número de pieza | Descripción | Fabricantes | |
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