AX1250ES
AXElite
2A Sink/Source Bus Termination RegulatorAX1250ES
2A Sink/Source Bus Termination Regulator
GENERAL DESCRIPTION The AX1250ES is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2
AX1250S
1.5A Sink/Source Bus Termination RegulatorAX1250S
1.5A Sink/Source Bus Termination Regulator
GENERAL DESCRIPTION AX1250S is a linear regulator designed as a cost-effective solution for active termination of DDR SDRAM. The converting voltage range is from 1.3V to 5.5V into a desired output voltage, which is adjusted by two external resi
AXElite
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