ADSP-21060L
Analog Devices
ADSP-2106x SHARC DSP Microcomputer Familya
SUMMARY High Performance Signal Processor for Communications, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive I/O 32-Bit IEEE Floating-Point Computation Units— Mu
ADSP-21060L
ANALOG DEVICES
SHARC ProcessorSHARC Processor
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
SUMMARY
High performance signal processor for communications, graphics and imaging applications Super Harvard Architecture 4 independent buses for dual data fetch, instructi
ADSP-21060LAB-160
Analog Devices
ADSP-2106x SHARC DSP Microcomputer Familya
SUMMARY High Performance Signal Processor for Communications, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive I/O 32-Bit IEEE Floating-Point Computation Units— Mu
ADSP-21060LC
ANALOG DEVICES
SHARC ProcessorSHARC Processor
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
SUMMARY
High performance signal processor for communications, graphics and imaging applications Super Harvard Architecture 4 independent buses for dual data fetch, instructi
ADSP-21060LKB-160
Analog Devices
ADSP-2106x SHARC DSP Microcomputer Familya
SUMMARY High Performance Signal Processor for Communications, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive I/O 32-Bit IEEE Floating-Point Computation Units— Mu
ADSP-21060LKS-133
Analog Devices
ADSP-2106x SHARC DSP Microcomputer Familya
SUMMARY High Performance Signal Processor for Communications, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive I/O 32-Bit IEEE Floating-Point Computation Units— Mu
ADSP-21060LKS-160
Analog Devices
ADSP-2106x SHARC DSP Microcomputer Familya
SUMMARY High Performance Signal Processor for Communications, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive I/O 32-Bit IEEE Floating-Point Computation Units— Mu