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a FEATURES 140 MSPS Guaranteed Conversion Rate 100 MSPS Low Cost Version Available 330 MHz Analog Bandwidth 1 V p-p Analog Input Range Internal 2.5 V Reference Differential or Single-Ended Clock Input 3.3 V/5.0 V Three-State CMOS Outputs Single or Demultiplexed Output Ports Data Clock Output Provide
01977-001 FEATURES IF sampling up to 350 MHz SNR: 67.5 dB, fIN up to Nyquist at 105 MSPS SFDR: 83 dBc, fIN = 70 MHz at 105 MSPS SFDR: 72 dBc, fIN = 150 MHz at 105 MSPS 2 V p-p analog input range On-chip clock duty cycle stabilization On-chip reference and track-and-hold SFDR optimization circuit Ex
FEATURES SNR = 65 dB @ fIN = 70 MHz @ 210 MSPS ENOB of 10.6 @ fIN = 70 MHz @ 210 MSPS (–0.5 dBFS) SFDR = 80 dBc @ fIN = 70 MHz @ 210 MSPS (–0.5 dBFS) Excellent linearity: DNL = ±0.3 LSB (typical) INL = ±0.5 LSB (typical) 2 output data options: Demultiplexed 3.3 V CMOS outputs each @ 105 MSPS I
8-Bit, 250 MSPS 3.3 V A/D Converter AD9481 FEATURES DNL = ±0.35 LSB INL = ±0.26 LSB Single 3.3 V supply operation (3.0 V to 3.6 V) Power dissipation of 439 mW at 250 MSPS 1 V p-p analog input range Internal 1.0 V reference Single-ended or differential analog inputs De-multiple
16-Bit, 80 MSPS/105 MSPS ADC AD9460 FEATURES 105 MSPS guaranteed sampling rate (AD9460-105) 79.4 dBFS SNR/91 dBc SFDR with 10 MHz input (3.4 V p-p input, 80 MSPS) 78.3 dBFS SNR/ with 170 MHz input (4.0 V p-p input, 80 MSPS) 77.8 dBFS SNR/87 dBc SFDR with 170 MHz input (3.4 V p-p
Preliminary Technical Data FEATURES 100 MSPS guaranteed sampling rate 100 dB two-tone SFDR with 30 MHz and 31 MHz 81.6 dB SNR with 30 MHz input (3.2 V p-p input, 80Msps) 90 dBc SFDR with30 MHz input (3.2 V p-p input, 80Msps) Excellent linearity DNL = ±0.5 LSB typical INL = ±3.0 LSB typical 2.3 W p
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PartNumber.co.kr | 2020 | 연락처 |