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v3.2 SX Family FPGAs u e ™ Leading Edge Performance • • • • 320 MHz Internal Performance 3.7 ns Clock-to-Out (Pin-to-Pin) 0.1 ns Input Setup 0.25 ns Clock Skew Features • • • • • • • • • • 66 MHz PCI CPLD and FPGA Integration Single-Chip Solution 100% Resource Utili
v3.1 54SX Family FPGAs Le a di ng E dg e P er f or m a nc e F ea t u r es • 320 MHz Internal Performance • 3.7 ns Clock-to-Out (Pin-to-Pin) • 0.1 ns Input Set-Up • 0.25 ns Clock Skew Sp e ci f ic at ion s • 66 MHz PCI • CPLD and FPGA Integration • Single Chip Solution • 100% Resou
v3.2 SX Family FPGAs u e ™ Leading Edge Performance • • • • 320 MHz Internal Performance 3.7 ns Clock-to-Out (Pin-to-Pin) 0.1 ns Input Setup 0.25 ns Clock Skew Features • • • • • • • • • • 66 MHz PCI CPLD and FPGA Integration Single-Chip Solution 100% Resource Utili
v5.1 SX-A Family FPGAs Leading-Edge Performance • • 250 MHz System Performance 350 MHz Internal Performance • • • • • • • • • • ™ Specifications • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops
v3.2 SX Family FPGAs u e ™ Leading Edge Performance • • • • 320 MHz Internal Performance 3.7 ns Clock-to-Out (Pin-to-Pin) 0.1 ns Input Setup 0.25 ns Clock Skew Features • • • • • • • • • • 66 MHz PCI CPLD and FPGA Integration Single-Chip Solution 100% Resource Utili
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