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80C186XL 80C188XL 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS Y Low Power Fully Static Versions of 80C186 80C188 Operation Modes Enhanced Mode DRAM Refresh Control Unit Power-Save Mode Direct Interface to 80C187 (80C186XL Only) Compatible Mode NMOS 80186 80188 Pin-for-Pin Replacement for Non-Numeri
80C186EC 80C188EC AND 80L186EC 80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS X Fully Static Operation X True CMOS Inputs and Outputs Y Integrated Feature Set Low-Power Static Enhanced 8086 CPU Core Two Independent DMA Supported UARTs each with an Integral Baud Rate Generator Four Independent
80C186EC 80C188EC AND 80L186EC 80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS X Fully Static Operation X True CMOS Inputs and Outputs Y Integrated Feature Set Low-Power Static Enhanced 8086 CPU Core Two Independent DMA Supported UARTs each with an Integral Baud Rate Generator Four Independent
80C186EC 80C188EC AND 80L186EC 80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS X Fully Static Operation X True CMOS Inputs and Outputs Y Integrated Feature Set Low-Power Static Enhanced 8086 CPU Core Two Independent DMA Supported UARTs each with an Integral Baud Rate Generator Four Independent
80C186EB 80C188EB AND 80L186EB 80L188EB 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS X Y X Full Static Operation True CMOS Inputs and Outputs Y Integrated Feature Set Low-Power Static CPU Core Two Independent UARTs each with an Integral Baud Rate Generator Two 8-Bit Multiplexed I O Ports Programmab
80C186EC 80C188EC AND 80L186EC 80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS X Fully Static Operation X True CMOS Inputs and Outputs Y Integrated Feature Set Low-Power Static Enhanced 8086 CPU Core Two Independent DMA Supported UARTs each with an Integral Baud Rate Generator Four Independent
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