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79RC32332  

IDT
IDT

79RC32332

IDT79RC32332

IDT79RC32334 and IDT79RC32332 Integrated Communications Processors (Y Revision) RISCore™ 32300 Family w w User Reference Manual w .D at June 2002 aS he et 2975 Stender Way, Santa Clara, California 95054 Telephone: (800) 345-7




관련 부품 79RC323 상세설명

79RC32364  

  
RISController Embedded 32-bit Microprocessor

RISControllerTM Embedded 32-bit Microprocessor, based on RISCore32300 79RC32364™ Features High-performance embedded RISController microprocessor, based on IDT RISCore32300TM 32-bit CPU core – Based on MIPS 32 RISC architecture with enhancements – Scalar 5-stage pipeline



IDT
IDT

PDF



79RC32355  

  
IDT Interprise Integrated Communications Processor

IDT Interprise Integrated Communications Processor TM TM 79RC32355 Features List RC32300 32-bit Microprocessor – Enhanced MIPS-II ISA – Enhanced MIPS-IV cache prefetch instruction – DSP Instructions – MMU with 16-entry TLB – 8KB Instruction Cache, 2-way set associati



Integrated Device Technology
Integrated Device Technology

PDF



79RC32355  

  
IDT Interprise Integrated Communications Processor

IDT Interprise Integrated Communications Processor TM TM 79RC32355 Features List RC32300 32-bit Microprocessor – Enhanced MIPS-II ISA – Enhanced MIPS-IV cache prefetch instruction – DSP Instructions – MMU with 16-entry TLB – 8KB Instruction Cache, 2-way set associati



Integrated Device Technology
Integrated Device Technology

PDF



79RC32351  

  
IDT Interprise Integrated Communications Processor

IDTTM InterpriseTM Integrated Communications Processor 79RC32351 Features List RC32300 32-bit Microprocessor – Enhanced MIPS-II ISA – Enhanced MIPS-IV cache prefetch instruction – DSP Instructions – MMU with 16-entry TLB – 8kB Instruction cache, 2-way set associative



Integrated Device Technology
Integrated Device Technology

PDF



79RC32334  

  
IDT Interprise Integrated Communications Processor

IDTTM InterpriseTM Integrated Communications Processor 79RC32334—Rev. Y RC32300 32-bit Microprocessor – Up to 150 MHz operation – Enhanced MIPS-II Instruction Set Architecture (ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions – Supports big or littl



Integrated Device Technology
Integrated Device Technology

PDF




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