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( DataSheet : ) ® 74VHC126 QUAD BUS BUFFERS (3-STATE) PRELIMINARY DATA s s s s s s s s s s HIGH SPEED: tPD = 3.8 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INP
74VHC126; 74VHCT126 Quad buffer/line driver; 3-state Rev. 01 — 13 August 2009 Product data sheet 1. General description The 74VHC126; 74VHCT126 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard N
74VHC125 — Quad Buffer with 3-STATE Outputs 74VHC125 Quad Buffer with 3-STATE Outputs December 2007 Features ■ High Speed: tPD = 3.8ns (Typ.) at VCC = 5V ■ Lower power dissipation: ICC = 4 µA (Max.) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (Min.) ■ Power down protecti
74VHC125; 74VHCT125 Quad buffer/line driver; 3-state Rev. 02 — 13 October 2009 Product data sheet 1. General description The 74VHC125; 74VHCT125 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard
74VHC125 QUAD BUS BUFFERS (3-STATE) s HIGH SPEED: tPD = 3.8ns (TYP.) at VCC = 5V s LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C s HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) s POWER DOWN PROTECTION ON INPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8mA (MIN) s BALANCED PROPAGAT
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