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74VHC00 — Quad 2-Input NAND Gate February 2008 74VHC00 Quad 2-Input NAND Gate Features ■ High Speed: tPD = 3.7ns (typ.) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (min.) ■ Power down protection is provided on all inputs ■ Low noise: VOLP = 0.8V (max) ■ Low power dissip
74VHC00 — Quad 2-Input NAND Gate February 2008 74VHC00 Quad 2-Input NAND Gate Features ■ High Speed: tPD = 3.7ns (typ.) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (min.) ■ Power down protection is provided on all inputs ■ Low noise: VOLP = 0.8V (max) ■ Low power dissip
74VHC00 QUAD 2-INPUT NAND GATE s HIGH SPEED: tPD = 3.7ns (TYP.) at VCC = 5V s LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C s HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) s POWER DOWN PROTECTION ON INPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8mA (MIN) s BALANCED PROPAGATION D
74VHC00 — Quad 2-Input NAND Gate February 2008 74VHC00 Quad 2-Input NAND Gate Features ■ High Speed: tPD = 3.7ns (typ.) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (min.) ■ Power down protection is provided on all inputs ■ Low noise: VOLP = 0.8V (max) ■ Low power dissip
74VHC00 QUAD 2-INPUT NAND GATE s HIGH SPEED: tPD = 3.7ns (TYP.) at VCC = 5V s LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C s HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) s POWER DOWN PROTECTION ON INPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8mA (MIN) s BALANCED PROPAGATION D
74VHC00 — Quad 2-Input NAND Gate February 2008 74VHC00 Quad 2-Input NAND Gate Features ■ High Speed: tPD = 3.7ns (typ.) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (min.) ■ Power down protection is provided on all inputs ■ Low noise: VOLP = 0.8V (max) ■ Low power dissip
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