파트넘버.co.kr 74VHC00SJ 데이터시트 검색

74VHC00SJ 전자부품 데이터시트



74VHC00SJ 전자부품 회로 및
기능 검색 결과



74VHC00SJ  

Fairchild Semiconductor
Fairchild Semiconductor

74VHC00SJ

Quad 2-Input NAND Gate

74VHC00 — Quad 2-Input NAND Gate February 2008 74VHC00 Quad 2-Input NAND Gate Features ■ High Speed: tPD = 3.7ns (typ.) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (min.) ■ Power down protection is provided on all inputs ■ Low noise




관련 부품 74VHC00 상세설명

74VHC00N  

  
Quad 2-Input NAND Gate

74VHC00 — Quad 2-Input NAND Gate February 2008 74VHC00 Quad 2-Input NAND Gate Features ■ High Speed: tPD = 3.7ns (typ.) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (min.) ■ Power down protection is provided on all inputs ■ Low noise: VOLP = 0.8V (max) ■ Low power dissip



Fairchild Semiconductor
Fairchild Semiconductor

PDF



74VHC00MTC  

  
Quad 2-Input NAND Gate

74VHC00 — Quad 2-Input NAND Gate February 2008 74VHC00 Quad 2-Input NAND Gate Features ■ High Speed: tPD = 3.7ns (typ.) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (min.) ■ Power down protection is provided on all inputs ■ Low noise: VOLP = 0.8V (max) ■ Low power dissip



Fairchild Semiconductor
Fairchild Semiconductor

PDF



74VHC00T  

  
QUAD 2-INPUT NAND GATE

74VHC00 QUAD 2-INPUT NAND GATE s HIGH SPEED: tPD = 3.7ns (TYP.) at VCC = 5V s LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C s HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) s POWER DOWN PROTECTION ON INPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8mA (MIN) s BALANCED PROPAGATION D



STMicroelectronics
STMicroelectronics

PDF



74VHC00M  

  
Quad 2-Input NAND Gate

74VHC00 — Quad 2-Input NAND Gate February 2008 74VHC00 Quad 2-Input NAND Gate Features ■ High Speed: tPD = 3.7ns (typ.) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (min.) ■ Power down protection is provided on all inputs ■ Low noise: VOLP = 0.8V (max) ■ Low power dissip



Fairchild Semiconductor
Fairchild Semiconductor

PDF



74VHC00M  

  
QUAD 2-INPUT NAND GATE

74VHC00 QUAD 2-INPUT NAND GATE s HIGH SPEED: tPD = 3.7ns (TYP.) at VCC = 5V s LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C s HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) s POWER DOWN PROTECTION ON INPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8mA (MIN) s BALANCED PROPAGATION D



STMicroelectronics
STMicroelectronics

PDF



74VHC00  

  
Quad 2-Input NAND Gate

74VHC00 — Quad 2-Input NAND Gate February 2008 74VHC00 Quad 2-Input NAND Gate Features ■ High Speed: tPD = 3.7ns (typ.) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (min.) ■ Power down protection is provided on all inputs ■ Low noise: VOLP = 0.8V (max) ■ Low power dissip



Fairchild Semiconductor
Fairchild Semiconductor

PDF




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