파트넘버.co.kr 74S112 데이터시트 검색

74S112 전자부품 데이터시트



74S112 전자부품 회로 및
기능 검색 결과



74S112  

Fairchild Semiconductor
Fairchild Semiconductor

74S112

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop

DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised April 2000 DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs Gener



74S112  

TW
TW

74S112

STTL double-J-K flip-flop

54S112/74S112 STTL 型双 J-K 触发器 (负沿触发、 带清零和预置) 典型参数: f 工作频率=125MHz Pd=75mW 外引线排列图 逻辑图 功能表 输 预置 PRE 入 时钟 输 K × × × L L H H × 出 清除 CLR CLK × × × ↓



  [1] 




사이트 맵

0    1    2    3    4    5    6    7    8    9    A    B    C    

D    E    F    G    H    I    J    K    L    M    N    O

    P    Q    R    S    T    U    V    W    X    Y    Z


PartNumber.co.kr   |  2020    |  연락처