74S112
Fairchild Semiconductor
Dual Negative-Edge-Triggered Master-Slave J-K Flip-FlopDM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
August 1986 Revised April 2000
DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
Gener
74S112
TW
STTL double-J-K flip-flop54S112/74S112 STTL 型双 J-K 触发器 (负沿触发、 带清零和预置) 典型参数: f 工作频率=125MHz Pd=75mW 外引线排列图
逻辑图
功能表
输 预置
PRE
入 时钟
输 K × × × L L H H ×
出
清除
CLR
CLK
× × × ↓