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DM74LS503 8-Bit Successive Approximation Register March 1989 Revised March 2000 DM74LS503 8-Bit Successive Approximation Register (with Expansion Control) General Description The DM74LS503 register has an active LOW Enable (E) input that is used in cascading two or more packages for longer word l
SN54/74LS569A FOUR-BIT UP/DOWN COUNTER WITH THREE-STATE OUTPUTS The SN54 / 74LS569A is designed as programmable up/down BCD and Binary counters respectively. These devices have 3-state outputs for use in bus organized systems. With the exception of output enable (OE) and asynchronous clear (ACLR), a
DM54LS503 DM74LS503 8-Bit Successive Approximation Register (with Expansion Control) April 1992 DM54LS503 DM74LS503 8-Bit Successive Approximation Register (with Expansion Control) General Description The ’LS503 register is basically the same as the ’LS502 except that it has an active LOW Ena
SN54/74LS569A FOUR-BIT UP/DOWN COUNTER WITH THREE-STATE OUTPUTS The SN54 / 74LS569A is designed as programmable up/down BCD and Binary counters respectively. These devices have 3-state outputs for use in bus organized systems. With the exception of output enable (OE) and asynchronous clear (ACLR), a
SN54/74LS54 3-2-2-3-INPUT AND-OR-INVERT GATE 3-2-2-3-INPUT AND-OR-INVERT GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 14 1 2 3 4 5 6 7 GND 1 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSX
Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) DP-14 Conforms Conforms 0.97 g Unit: mm 10.06 10.5 Max 14 8 5.5 1 7 *0.22 ± 0.05 0.20
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