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DM74LS136 Quad 2-Input Exclusive-OR Gate with Open-Collector Outputs October 1988 Revised March 2000 DM74LS136 Quad 2-Input Exclusive-OR Gate with Open-Collector Outputs General Description This device contains four independent gates, each of which performs the logic exclusive-OR function. Orderi
Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) DP-14 Conforms Conforms 0.97 g Unit: mm 10.06 10.5 Max 14 8 5.5 1 7 *0.22 ± 0.05 0.20
54LS138 DM54LS138 DM74LS138 54LS139 DM54LS139 DM74LS139 Decoders Demultiplexers June 1989 54LS138 DM54LS138 DM74LS138 54LS139 DM54LS139 DM74LS139 Decoders Demultiplexers General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing
SN74LS132 Quad 2-Input Schmitt Trigger NAND Gate The SN74LS132 contains four 2-Input NAND Gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Additionall
SN54/74LS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES 3-LINE TO 8-LINE DECODERS/ DEMULTIPLEXERS WITH ADDRESS LATCHES DATA OUTPUTS VCC 16 Y0 15 Y0 A B C GL G2 G1 Y1 14 Y1 Y2 13 Y2 Y3 12 Y3 Y4 11 Y4 Y5 10 Y5 Y6 Y7 16 1 LOW POWER SCHOTTKY Y6 9 J SUFFIX CERAMIC CASE 620-09 1 A 2
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