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Datasheet 74LS11 Equivalent ( PDF ) |
| N.º | Número de pieza | Descripción | Fabricantes | |
| 5 | 74LS11 | Triple 3-Input AND Gate DM74LS11 Triple 3-Input AND Gate
August 1986 Revised March 2000
DM74LS11 Triple 3-Input AND Gate
General Description
This device contains three independent gates each of which performs the logic AND function.
Ordering Code:
Order Number DM74LS11M DM74LS11N Package Number M14A N14A Package Descrip |
 Fairchild Semiconductor |
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| 4 | 74LS112 | Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) 19.20 20.00 Max 16 9 7.40 Max 6.30
Unit: mm
1 1.3
1.11 Max
8
0.51 Min
2.54 Min 5.06 Max
7.62
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
Hitachi Code JEDEC EIAJ Weight (reference value)
+ 0.13
DP-16 Conforms Conforms 1.07 g
Unit: mm
10.06 10.5 Max 16 9
5.5
1
*0.22 ± 0.05 0.20 |
 Hitachi Semiconductor |
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| 3 | 74LS112A | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed t |
 Motorola Semiconductors |
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| 2 | 74LS112A | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
August 1986 Revised March 2000
DM74LS112A
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
General Description
This device contains |
Fairchild Semiconductor |
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