파트넘버.co.kr 74LS10 데이터시트 검색

74LS10 전자부품 데이터시트



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74LS10  

ON Semiconductor
ON Semiconductor

74LS10

TRIPLE 3-INPUT NAND GATE

SN54/74LS10 TRIPLE 3-INPUT NAND GATE TRIPLE 3-INPUT NAND GATE VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN



74LS10  

Fairchild Semiconductor
Fairchild Semiconductor

74LS10

Triple 3-Input NAND Gate

DM74LS10 Triple 3-Input NAND Gate August 1986 Revised March 2000 DM74LS10 Triple 3-Input NAND Gate General Description This device contains three independent gates each of which performs the logic NAND function. Ordering Code: Order Number DM74LS10M DM74LS1



74LS107  

ETC
ETC

74LS107

DM74LS107

DM54LS107A DM74LS107A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs June 1989 DM54LS107A DM74LS107A Dual Negative-EdgeTriggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Descripti



74LS109  

Agere Systems
Agere Systems

74LS109

Dual J-K Flip-Flop




74LS109A  

ON Semiconductor
ON Semiconductor

74LS109A

LOW POWER SCHOTTKY

SN74LS109A Dual JK Positive Edge-Triggered Flip-Flop The SN74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The



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