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Datasheet 74HC73 Equivalent ( PDF ) |
| N.º | Número de pieza | Descripción | Fabricantes | |
| 2 | 74HC73 | Dual JK flip-flop 74HC73
Dual JK flip-flop with reset; negative-edge trigger
Rev. 5 — 2 December 2015
Product data sheet
1. General description
The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inpu |
 NXP Semiconductors |
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| 1 | 74HC73 | Dual JK flip-flop with reset negative-edge trigger 74HC73
Dual JK flip-flop with reset; negative-edge trigger
Rev. 03 — 12 November 2004 Product data sheet
1. General description
The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no |
 Philips |
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