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Datasheet 74F113 Equivalent ( PDF ) |
| N.º | Número de pieza | Descripción | Fabricantes | |
| 5 | 74F113 | Dual J-K negative edge-triggered flip-flops without reset INTEGRATED CIRCUITS
74F113 Dual J-K negative edge-triggered flip-flops without reset
Product specification IC15 Data Handbook 1991 Feb 14
Philips Semiconductors
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flops without reset
74F113
FEATURE
• Industria |
 NXP Semiconductors |
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| 4 | 74F113 | Dual JK Negative Edge-Triggered Flip-Flop 74F113 Dual JK Negative Edge-Triggered Flip-Flop
April 1988 Revised July 1999
74F113 Dual JK Negative Edge-Triggered Flip-Flop
General Description
The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of th |
 Fairchild Semiconductor |
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| 3 | 74F113PC | Dual JK Negative Edge-Triggered Flip-Flop 74F113 Dual JK Negative Edge-Triggered Flip-Flop
April 1988 Revised July 1999
74F113 Dual JK Negative Edge-Triggered Flip-Flop
General Description
The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of th |
Fairchild Semiconductor |
|
| 2 | 74F113SC | Dual JK Negative Edge-Triggered Flip-Flop 74F113 Dual JK Negative Edge-Triggered Flip-Flop
April 1988 Revised July 1999
74F113 Dual JK Negative Edge-Triggered Flip-Flop
General Description
The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of th |
Fairchild Semiconductor |
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