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v5.1 SX-A Family FPGAs Leading-Edge Performance • • 250 MHz System Performance 350 MHz Internal Performance • • • • • • • • • • ™ Specifications • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops
v2.0 General-Purpose SDRAM Controller SD R A M Co n t r o l l er Fu nc t i o na l D es cr i p t i o n The general-purpose SDRAM controller is designed to provide simplified control of many different sizes of SDRAMs. The controller architecture provides control for data bursts by linearly increment
54S138/74S138 STTL 型 3 线-8 线译码器/解调器 特点: ·专为高速存贮译码和数据传输系 统而设计 ·有三个赋能输入,简化了级联与/ 或数据接收 ·高性能的肖特基钳位技术 逻辑图 典型参数: tpd=8ns(使能) tpd=7ns(选择) Pd=245mW 外引线排
54S10/74S10 STTL 型三 3 输入与非门 典型参数: tpd=3ns Pd=19mW/每门 线路图(1/3) 逻辑符号 逻辑式: 外引线排列图: 逻辑表: 输入 B H × L × 输出 Y L H H H A H L × × C H × × L 推荐工作条件 74Ⅱ 符号 Vcc VIH VIL IOH IOL TA 参数名称 最小
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