54LS75
Motorola Semiconductors
4-BIT D LATCH4-BIT D LATCH
The TTL/MSI SN54 / 74LS75 and SN54 / 74LS77 are latches used as temporary storage for binary information between processing units and input /output or indicator units. Information present at a data (D) input is transferred to the Q output when th
54LS85
4-Bit Magnitude Comparators54LS85 DM54LS85 DM74LS85 4-Bit Magnitude Comparators
June 1989
54LS85 DM54LS85 DM74LS85 4-Bit Magnitude Comparators
General Description
These 4-bit magnitude comparators perform comparison of straight binary or BCD codes Three fully-decoded decisions about two 4-bit words (A B) are made and are ex
National Semiconductor
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54LS367A
Hex TRI-STATE Buffers54LS367A DM54LS367A DM74LS367A Hex TRI-STATE Buffers
May 1989
54LS367A DM54LS367A DM74LS367A Hex TRI-STATE Buffers
General Description
This device contains six independent gates each of which performs a non-inverting buffer function The outputs have the TRI-STATE feature When enabled the outputs
National Semiconductor
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