파트넘버.co.kr 2N3810 데이터시트 검색

2N3810 전자부품 데이터시트



2N3810 전자부품 회로 및
기능 검색 결과



2N3810  

Motorola Semiconductors
Motorola Semiconductors

2N3810

(2N3806 - 2N3811) Dual AMplifier Transistors

w w a D . w S a t e e h U 4 t m o .c w w .D w t a S a e h U 4 t e .c m o w w w .D a S a t e e h U 4 t m o .c



2N3810  

NES
NES

2N3810

PNP Silicon Dual Amplifier Transistor




2N3810  

Microsemi Corporation
Microsemi Corporation

2N3810

PNP SILICON DUAL TRANSISTOR

TECHNICAL DATA PNP SILICON DUAL TRANSISTOR Qualified per MIL-PRF-19500/336 Devices 2N3810 2N3810L 2N3810U 2N3811 2N3811L 2N3811U Qualified Level JAN JANTX JANTXV MAXIMUM RATINGS Ratings Collector-Emitter Voltage Collector-Base Voltage Emitter-Base Voltage Col



2N3810  

Central Semiconductor
Central Semiconductor

2N3810

SILICON DUAL PNP TRANSISTORS

2N3810 2N3810A SILICON DUAL PNP TRANSISTORS w w w. c e n t r a l s e m i . c o m DESCRIPTION: The CENTRAL SEMICONDUCTOR 2N3810 and 2N3810A are dual silicon PNP transistors manufactured by the epitaxial planar process utilizing two individual chips mounted in



2N3810  

Semicoa Semiconductor
Semicoa Semiconductor

2N3810

Type 2N3810 Geometry 0220 Polarity PNP

Data Sheet No. 2N3810 Type 2N3810 Geometry 0220 Polarity PNP Qual Level: JAN - JANS Features: • • • • Two electrically isolated, matched PNP transistors as one dual unit. Housed in TO-78 case. Also available in chip form using the 0220 chip geometry.



2N3810A  

Motorola Semiconductors
Motorola Semiconductors

2N3810A

(2N3806 - 2N3811) Dual AMplifier Transistors

w w a D . w S a t e e h U 4 t m o .c w w .D w t a S a e h U 4 t e .c m o w w w .D a S a t e e h U 4 t m o .c



2N3810A  

NES
NES

2N3810A

PNP Silicon Dual Amplifier Transistor




2N3810A  

Central Semiconductor
Central Semiconductor

2N3810A

SILICON DUAL PNP TRANSISTORS

2N3810 2N3810A SILICON DUAL PNP TRANSISTORS w w w. c e n t r a l s e m i . c o m DESCRIPTION: The CENTRAL SEMICONDUCTOR 2N3810 and 2N3810A are dual silicon PNP transistors manufactured by the epitaxial planar process utilizing two individual chips mounted in



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