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CA1394 반도체 회로 부품 판매점

(CA1391 / CA1394) TV Horizontal Processors



Harris Corporation 로고
Harris Corporation
CA1394 데이터시트, 핀배열, 회로
CA1391, CA1394
May 1999
CNalOl CoRerEneCtOmrOaBalMSiAl:MOpELcpeENlincTDtaEaEtpiDPopRnR@OsEhD1Pa-UL8rrAC0is0CT.-Ec4oM4m2E-7N7T47
TV Horizontal Processors
[ /Title
(CA13
91,
CA139
4)
/Sub-
ject
(TV
Hori-
zontal
Proces-
sors)
/Autho
r ()
/Key-
words
(Har-
ris
Semi-
con-
ductor,
TV
hori-
zontal
proces-
sor,
hori-
zontal
oscilla-
tor,
hori-
zontal
driver,
phase
detec-
tor,
AFC
cir-
cuit,
AGC
cir-
cuit,
Features
Description
• CA1391E - Positive Horizontal Sawtooth Input
• CA1394E - Negative Horizontal Sawtooth Input
• Internal Shunt Regulator
• Linear Balanced Phase Detector
• Preset Hold Control Capability
• Pull-In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±300Hz (Typ)
• Low Thermal Frequency Drift
• Small Static Phase Error
• Variable Output Duty Cycle
The Harris CA1391E and CA1394E are monolithic
integrated circuits designed for use in the low-level
horizontal section of monochrome or color television
receivers. Functions include a phase detector, an oscillator,
a regulator, and a pre-driver.
The CA1391E and CA1394E are electrically equivalent and
pin compatible with industry types 1391 and 1394 in similar
packages.
Part Number Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
CA1391E
0 to 85 8 Ld PDIP
PKG.
NO.
E8.3
• Adjustable DC Loop Gain
CA1394E
0 to 85 8 Ld PDIP
E8.3
Pinout
CA1391, CA1394
(PDIP)
TOP VIEW
OUT 1
GND 2
SYNC
IN
HORIZ
IN
3
4
MARK-
8
SPACE
RATIO
7
OSC
TIMING
6 V+
PHASE
5 DETECT
OUT
Functional Diagram
PHASE
DETECTOR
OUTPUT
5
V+
6
OSCILLATOR
TIMING
7
PHASE
DETECTOR
OUT
OSCILLATOR
REGULATOR
MARK-SPACE
RATIO
8
4
HORIZONTAL
SAWTOOTH
INPUT
PHASE
DETECTOR
PRE-
DRIVER
3
SYNC
INPUT
2
GROUND
1
OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1999
8-9
File Number 981.4


CA1394 데이터시트, 핀배열, 회로
CA1391, CA1394
Absolute Maximum Ratings
DC Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA
DC Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Sync Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5VP-P
Sawtooth Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5VP-P
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications (See Figure 1)
PARAMETER
TEST CONDITIONS
TEMP. (oC)
MIN
TYP
MAX
UNITS
Supply Voltage
S1, S5, S6 = 2; S2, S3, S4, S7, S8 = 1
Measure Terminal 6 to GND
25 8 - 9 V
Free Running
Frequency -1%
S1, S5, S6 = 2; S2, S3, S4, S7, S8 = 1
Counter to Terminal 1
25
14734
-
16734
Hz
Output Leakage
S2, S3, S6, S8 = 1; S1, S4, S5, S7 = 2
Measure Terminal 1 to 25V
25 - 10 - mV
Output Saturation
S2, S3, S5, S6, S8 = 1; S1, S4, S7 = 2
Measure Terminal 1 to GND
25 - 60 - mV
Phase Detector Bias
S2, S5, S6, S8 = 1; S1, S3, S4, S7 = 2
Measure Terminal 3 to GND
25
- 1.9 -
V
Phase Detector Leak
S5, S8 = 1; S1, S2, S3, S4, S6, S7 = 2
Measure Terminal 5 to +4V
25 -2 - 2 mV
Phase Detector Low
S1, S5, S8 = 1; S2, S3, S4, S6, S7 = 2
Measure Terminal 5 to +4V
25
-0.55
-
-
V
(Note 2)
Phase Detector High
S1, S5, S6, S8 = 1; S2, S3, S4, S7 = 2
Measure Terminal 5 to +4V
25
+0.55
-
-
V
(Note 2)
Phase Detector Balance VDET2 + VDET3
Sync Diode
S1, S2, S3, S4, S6, S7 = 1; S5, S8 = 2
Static Phase Error
See Figure 3
25 -100 - 100 mV
25 0.3 - 1.2 V
25 - 0.5 - µs
Oscillator Pull In Range
- ±300 -
Hz
Oscillator Hold In Range
- ±900 -
Hz
NOTE:
2. Polarity reversed in the CA1391.
8-10




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CA1394 tv

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