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NXP Semiconductors |
Z0103MA0
4Q Triac
Rev. 01 — 3 January 2011
Product data sheet
1. Product profile
1.1 General description
Planar passivated sensitive gate four quadrant triac in a SOT54 (TO-92) plastic package
intended for use in applications requiring enhanced noise immunity and direct interfacing
to logic ICs and low power gate drivers.
1.2 Features and benefits
Direct interfacing to logic level ICs
Enhanced current surge capability
Enhanced noise immunity
High blocking voltage capability
Sensitive gate triggering in all four
quadrants
1.3 Applications
General purpose low power motor
control
Home appliances
Industrial process control
Low power AC Fan controllers
1.4 Quick reference data
Table 1. Quick reference data
Symbol Parameter
Conditions
VDRM
repetitive peak off-state
voltage
ITSM
non-repetitive peak
full sine wave; Tj(init) = 25 °C;
on-state current
tp = 20 ms; see Figure 4;
see Figure 5
IT(RMS)
RMS on-state current
full sine wave; Tlead ≤ 38 °C;
see Figure 3; see Figure 1;
see Figure 2
Static characteristics
IGT
gate trigger current
VD = 12 V; IT = 0.1 A; T2+ G+;
Tj = 25 °C; see Figure 7
VD = 12 V; IT = 0.1 A; T2+ G-;
Tj = 25 °C; see Figure 7
VD = 12 V; IT = 0.1 A; T2- G-;
Tj = 25 °C; see Figure 7
VD = 12 V; IT = 0.1 A; T2- G+;
Tj = 25 °C; see Figure 7
Min Typ Max Unit
- - 600 V
- - 12.5 A
- - 1A
0.2 -
0.2 -
0.2 -
0.2 -
3 mA
3 mA
3 mA
5 mA
Free Datasheet http://www.datasheet4u.com/
NXP Semiconductors
Z0103MA0
4Q Triac
2. Pinning information
Table 2.
Pin
1
2
3
Pinning information
Symbol Description
T2 main terminal 2
G gate
T1 main terminal 1
Simplified outline
Graphic symbol
T2
sym051
T1
G
3. Ordering information
321
SOT54 (TO-92)
Table 3. Ordering information
Type number
Package
Name
Z0103MA0
TO-92
4. Limiting values
Description
plastic single-ended leaded (through hole) package; 3 leads
Version
SOT54
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min Max Unit
VDRM
IT(RMS)
repetitive peak off-state voltage
RMS on-state current
full sine wave; Tlead ≤ 38 °C; see Figure 3;
see Figure 1; see Figure 2
-
-
600 V
1A
ITSM
non-repetitive peak on-state
full sine wave; Tj(init) = 25 °C; tp = 20 ms;
-
12.5 A
current
see Figure 4; see Figure 5
I2t
dIT/dt
I2t for fusing
rate of rise of on-state current
full sine wave; Tj(init) = 25 °C; tp = 16.7 ms
tp = 10 ms; sine-wave pulse
IT = 1 A; IG = 20 mA; dIG/dt = 100 mA/µs;
T2+ G+
-
-
-
13.8
0.78
50
A
A2s
A/µs
IT = 1 A; IG = 20 mA; dIG/dt = 100 mA/µs;
T2+ G-
-
50 A/µs
IT = 1 A; IG = 20 mA; dIG/dt = 100 mA/µs;
T2- G-
-
50 A/µs
IT = 1 A; IG = 20 mA; dIG/dt = 100 mA/µs;
T2- G+
-
20 A/µs
IGM
PGM
PG(AV)
Tstg
Tj
peak gate current
peak gate power
average gate power
storage temperature
junction temperature
over any 20 ms period
- 1A
- 2W
- 0.1 W
-40 150 °C
- 125 °C
Z0103MA0
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
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