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PDF 8T49N286 Data sheet ( Hoja de datos )
| Número de pieza | 8T49N286 | |
| Descripción | NG Octal Universal Frequency Translator | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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FemtoClock® NG Octal Universal
Frequency Translator
8T49N286
Datasheet
General Description
The 8T49N286 has two independent, fractional-feedback PLLs that
can be used as jitter attenuators and frequency translators. It is
equipped with six integer and two fractional output dividers, allowing
the generation of up to eight different output frequencies, ranging
from 8kHz to 1GHz. Four of these frequencies are completely
independent of each other and the inputs. The other four are related
frequencies. The eight outputs may select among LVPECL, LVDS,
HCSL or LVCMOS output levels.
This functionality makes it ideal to be used in any frequency
translation application, including 1G, 10G, 40G and 100G
Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T
G.709 (2009) FEC rates. The device may also behave as a frequency
synthesizer.
The 8T49N286 accepts up to four differential or single-ended input
clocks and a crystal input. Each of the two internal PLLs can lock to
different input clocks which may be of independent frequencies. The
other two input clocks are intended for redundant backup of the
primary clocks and must be related in frequency to their primary.
The device supports hitless reference switching between input
clocks. The device monitors all input clocks for Loss of Signal (LOS),
and generates an alarm when an input clock failure is detected.
Automatic and manual hitless reference switching options are
supported. LOS behavior can be set to support gapped or un-gapped
clocks.
The 8T49N286 supports holdover for each PLL. The holdover has an
initial accuracy of ±50ppB from the point where the loss of all
applicable input reference(s) has been detected. It maintains a
historical average operating point for each PLL that may be returned
to in holdover at a limited phase slope.
The device places no constraints on input to output frequency
conversion, supporting all FEC rates, including the new revision of
ITU-T Recommendation G.709 (2009), most with 0ppm conversion
error.
Each PLL has a register-selectable loop bandwidth from 1.4Hz to
360Hz.
Each output supports individual phase delay settings to allow
output-output alignment.
The device supports Output Enable inputs and Lock, Holdover and
LOS status outputs.
The device is programmable through an I2C interface. It also supports
I2C master capability to allow the register configuration to be read
from an external EEPROM. The user may select whether the
programming interface uses I2C protocols or SPI protocols, however
in SPI mode, read from the external EEPROM is not supported.
Applications
• OTN or SONET / SDH equipment Line cards (up to OC-192, and
supporting FEC ratios)
• OTN de-mapping (Gapped Clock and DCO mode)
• Gigabit and Terabit IP switches / routers including support of
Synchronous Ethernet
• SyncE (G.8262) applications
• Wireless base station baseband
• Data communications
• 100G Ethernet
Features
• Supports SDH/SONET and Synchronous Ethernet clocks
including all FEC rate conversions
• <0.3ps RMS Typical Jitter (including spurs), 12kHz to 20MHz
• Operating modes: locked to input signal, holdover and free-run
• Initial holdover accuracy of ±50ppb
• Accepts up to four LVPECL, LVDS, LVHSTL, HCSL or LVCMOS
input clocks
• Accepts frequencies ranging from 8kHz up to 875MHz
• Auto and manual input clock selection with hitless switching
• Clock input monitoring, including support for gapped clocks
• Phase-Slope Limiting and Fully Hitless Switching options to
control output phase transients
• Operates from a 10MHz to 40MHz fundamental-mode crystal
• Generates 8 LVPECL / LVDS / HCSL or 16 LVCMOS output
clocks
• Output frequencies ranging from 8kHz up to 1.0GHz (diff)
• Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
• Eight General Purpose I/O pins with optional support for status
and control
• Eight Output Enable control inputs
• Lock, Holdover and Loss-of-Signal status outputs
• Open-drain Interrupt pin
• Write-protect pin to prevent configuration registers being altered
• Nine programmable loop bandwidth settings for each PLL from
1.4Hz to 360Hz.
• Optional Fast Lock function
• Programmable output phase delays in steps as small as 16ps
• Register programmable through I2C / SPI or via external I2C
EEPROM
• Bypass clock paths for system tests
• Power supply modes:
VCC / VCCA / VCCO
3.3V / 3.3V / 3.3V
3.3V / 3.3V / 2.5V
3.3V / 3.3V / 1.8V (LVCMOS)
2.5V / 2.5V / 3.3V
2.5V / 2.5V / 2.5V
2.5V / 2.5V / 1.8V (LVCMOS)
• -40°C to 85°C ambient operating temperature
• Package: 72QFN, lead-free RoHs (6)
©2016 Integrated Device Technology, Inc.
1
Revision 7, October 27, 2016
1 page  
8T49N286 Datasheet
Number
6, 30, 36, 55, 61,
ePAD
Name
VEE
Type
Power
Description
Negative supply voltage. All VEE pins and EPAD must be connected before
any positive supply voltage is applied.
15
22
1
19, 20, 21, 25
66, 70, 71, 72
64
58
33
27
52
48
44
40
68,
67
VCC
VCC
VCCA
VCCA
VCCA
VCCO0
VCCO1
VCCO2
VCCO3
VCCO4
VCCO5
VCCO6
VCCO7
CAP0,
CAP0_REF
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Analog
Core and digital function supply voltage.
Core and digital functions supply voltage.
Analog function supply voltage for core analog functions.
Analog function supply voltage for analog functions associated with PLL1.
Analog function supply voltage for analog functions associated with PLL0.
High-speed output supply voltage for output pair Q0, nQ0.
High-speed output supply voltage for output pair Q1, nQ1.
High-speed output supply voltage for output pair Q2, nQ2.
High-speed output supply voltage for output pair Q3, nQ3.
High-speed output supply voltage for output pair Q4, nQ4.
High-speed output supply voltage for output pair Q5, nQ5.
High-speed output supply voltage for output pair Q6, nQ6.
High-speed output supply voltage for output pair Q7, nQ7.
PLL0 External Capacitance.
23,
24
CAP1,
CAP1_REF
Analog
PLL1 External Capacitance.
4 nc Unused No connect.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
©2016 Integrated Device Technology, Inc.
5
Revision 7, October 27, 2016
5 Page 
8T49N286 Datasheet
Output Drivers
The Q0 to Q7 clock outputs are provided with register-controlled
output drivers. By selecting the output drive type in the appropriate
register, any of these outputs can support LVCMOS, LVPECL, HCSL
or LVDS logic levels.
The operating voltage ranges of each output is determined by its
independent output power pin (VCCO) and thus each can have
different output voltage levels. Output voltage levels of 2.5V or 3.3V
are supported for differential operation and LVCMOS operation. In
addition, LVCMOS output operation supports 1.8V VCCO.
Each output may be enabled or disabled by register bits and/or GPIO
pins configured as Output Enables. The outputs will be enabled if the
register bit and the associated OE pin are both asserted (high). When
disabled an output will be in a high impedance state.
LVCMOS Operation
When a given output is configured to provide LVCMOS levels, then
both the Q and nQ outputs will toggle at the selected output
frequency. All the previously described configuration and control
apply equally to both outputs. Frequency, phase alignment, voltage
levels and enable / disable status apply to both the Q and nQ pins.
When configured as LVCMOS, the Q and nQ outputs can be selected
to be phase-aligned with each other or inverted relative to one
another. Phase-aligned outputs will have increased simultaneous
switching currents which can negatively affect phase noise
performance and power consumption. It is recommended that use of
this selection be kept to a minimum.
Power-Saving Modes
To allow the device to consume the least power possible for a given
application, the following functions are included under register
control:
• PLL1 may be shut down.
• Any unused output, including all output divider and phase
adjustment logic, can be individually powered-off.
• Clock gating on logic that is not being used.
Status / Control Signals and Interrupts
General-Purpose I/Os & Interrupts
The 8T49N286 provides eight General Purpose Input / Output
(GPIO) pins for miscellaneous status & control functions. Each GPIO
may be configured as an input or an output. Each GPIO may be
directly controlled from register bits or be used as a predefined
function as shown in Table 4. Note that the default state prior to
configuration being loaded from internal OTP or external EEPROM
will be to set each GPIO to function as an Output Enable.
Table 4. GPIO Configuration
GPIO
Pin
7
6
5
4
3
2
1
0
Configured as Input
Fixed Function
Output
Enable
(default)
Clock
Select
General
Purpose
OE[7] CSEL1[1] GPI[7]
OE[6] CSEL0[1] GPI[6]
OE[5] - GPI[5]
OE[4] - GPI[4]
OE[3] CSEL1[0] GPI[3]
OE[2] CSEL0[0] GPI[2]
OE[1] - GPI[1]
OE[0] - GPI[0]
Configured as Output
Fixed
Function
LOS[3]
LOS[2]
LOS[1]
HOLD[1]
LOL[1]
LOS[0]
HOLD[0]
LOL[0]
General
Purpose
GPO[7]
GPO[6]
GPO[5]
GPO[4]
GPO[3]
GPO[2]
GPO[1]
GPO[0]
If used in the Fixed Function mode of operation, the GPIO bits will
reflect the real-time status of their respective status bits as shown in
Table 4. Note that the LOL signal represents the lock status of the
PLL. It does not account for the process of synchronization of the
output dividers associated with that PLL. The output dividers
programmed to operate from that PLL will automatically go through a
re-synchronization process when the PLL locks or re-locks or if the
user triggers a re-sync manually via register bit PLLn_SYN. This
synchronization process may result in a period of instability on the
affected outputs for a duration of up to 350ns after the re-lock (LOL
de-asserts) or the PLLn_SYN bit is de-asserted.
Interrupt Functionality
Interrupt functionality includes an interrupt status flag for each of PLL
Loss-of-Lock Status (LOL[1:0]), PLL Holdover Status (HOLD[1:0])
and Input Reference Status (LOS[3:0]) that is set whenever there is
an alarm on any of those signals. The Status Flag will remain set until
the alarm has been cleared and a ‘1’ has been written to the Status
Flag’s register location or if a reset occurs. Each Status Flag will also
have an Interrupt Enable bit that will determine if that Status Flag is
allowed to cause the Interrupt Status to be affected (enabled) or not
(disabled). All Interrupt Enable bits will be in the disabled state after
reset. The Device Interrupt Status flag and nINT output pin are
asserted if any of the enabled Interrupt Status flags are set.
Device Hardware Configuration
The 8T49N286 supports an internal One-Time Programmable (OTP)
memory that can be pre-programmed at the factory with one
complete device configuration. If the device is set to read a
configuration from an external, serial EEPROM, then the values read
will overwrite the OTP-defined values.
This configuration can be over-written using the serial interface once
reset is complete. Any configuration written via the programming
interface needs to be re-written after any power cycle or reset. Please
contact IDT if a specific factory-programmed configuration is desired.
©2016 Integrated Device Technology, Inc.
11
Revision 7, October 27, 2016
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 8T49N286.PDF ] | |
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