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PDF SY100ELT21L Data sheet ( Hoja de datos )
| Número de pieza | SY100ELT21L | |
| Descripción | 3.3V DIFFERENTIAL LVPECL-to-LVTTL TRANSLATOR | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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3.3V DIFFERENTIAL
LVPECL-to-LVTTL
TRANSLATOR
ClockWorks™
SY10ELT21L
SY100ELT21L
FEATURES
s 3.3V power supply
s 2.0ns typical propagation delay
s Low power
s Differential LVPECL inputs
s 24mA TTL outputs
s Flow-through pinouts
s Available in 8-pin SOIC package
PIN CONFIGURATION/BLOCK DIAGRAM
NC 1
D2
PECL
D3
VBB 4
8 VCC
TTL 7 Q
6 NC
5 GND
DESCRIPTION
The SY10/100ELT21L are single differential LVPECL-
to-LVTTL translators using a single +3.3V power supply.
Because LVPECL (Low Voltage Positive ECL) levels are
used, only +3.3V and ground are required. The small
outline 8-lead SOIC package and low skew single gate
design make the ELT21L ideal for applications that require
the translation of a clock or data signal where minimal
space, low power, and low cost are critical.
VBB allows a differential, single-ended, or AC-coupled
interface to the device. If used, the VBB output should be
bypassed to VCC with 0.01µF capacitor.
Under open input conditions, the /D will be biased at a
VCC/2 voltage level and the D input will be pulled to
ground. This condition will force the Q output low to
provide added stability.
The ELT21L is available in both ECL standards: the
10ELT is compatible with positive ECL 10H logic levels,
while the 100ELT is compatible with positive ECL 100K
logic levels.
PIN NAMES
Pin
Q
D, /D
VCC
VBB
GND
Function
TTL Output
Differential LVPECL Inputs
+3.3V Supply
Reference Output
Ground
Rev.: B Amendment: /0
1 Issue Date: April 2000
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet SY100ELT21L.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| SY100ELT21L | 3.3V DIFFERENTIAL LVPECL-to-LVTTL TRANSLATOR | Micrel Semiconductor |
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